MT45V512KW16PEGA-70 WT Micron Technology Inc, MT45V512KW16PEGA-70 WT Datasheet - Page 15

• Manufacturer Part Number: MT45V512KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45V512KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Software Access to the Configuration Register
Figure 11:
PDF: 09005aef82f264f6/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. C 4/08 EN
Load Configuration Register
Notes:
The contents of the CR can be read or modified using a software access sequence. The
nature of this access mechanism can potentially eliminate the need for the ZZ# ball.
If the software-access mechanism is used, ZZ# can simply be tied to V
typically used for ZZ# control purposes will no longer be required. However, ZZ# should
not be tied to V
the software-access sequence.
The CR is loaded using a four-step sequence consisting of two READ operations followed
by two WRITE operations (see Figure 11). The READ sequence is virtually identical
except that an asynchronous READ is performed during the fourth operation (see
Figure 12 on page 16).
The address used during all READ and WRITE operations is the highest address of the
PSRAM device being accessed (7FFFFh for 8Mb devices); the content of this address is
not changed by using the software-access sequence. The data bus is used to transfer
data into or out of bits[15:0] of the CR.
Writing to the CR using the software-access sequence modifies the function of the ZZ#
ball. After the software sequence loads the CR, the level of the ZZ# ball no longer enables
PAR operation. PAR operation is updated whenever the software-access sequence loads
a new value into the CR. This ZZ# functionality will remain active until the next time the
device is powered up. The operation of the ZZ# ball is not affected if the software-access
sequence is only used to read the contents of the CR. Use of the software-access
sequence does not affect the performance of standard (ZZ#-controlled) CR loading.
LB#/UB#
1. It is possible that the data stored at the highest memory location will be altered if the data
Address
Data
WE#
at the falling edge of WE# is not 0000h.
OE#
CE#
Address
(MAX)
XXXXh
READ
CC
8Mb: 3.0V Core Async/Page PSRAM Memory 512K x 16
Q if the system will use DPD; DPD cannot be enabled or disabled using
Address
XXXXh
(MAX)
READ
15
CR: 0000h
Address
WRITE
(MAX)
0ns (MIN), see Note 1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WRITE
Address
CR value
(MAX)
Don’t Care
in
Configuration Register Operation
©2007 Micron Technology, Inc. All rights reserved.
CC
Q; the port line