MCIMX27MJP4A Freescale, MCIMX27MJP4A Datasheet - Page 29

• Manufacturer Part Number: MCIMX27MJP4A
• Manufacturer: Freescale

Specifications of MCIMX27MJP4A

• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
Power_on_reset
osc32K_bypass
BOOT [3:0]
JTAG_CTRL
TRST
TDO
TDI
TCK
TMS
RTCK
SD1_CMD
SD1_CLK
SD1_D[3:0]
SD2_CMD
SD2_CLK
SD2_D[3:0]
SD3_CMD
SD3_CLK
Pad Name
Table 3. i.MX27/MX27L Signal Descriptions (continued)
(Note: in the RTC power domain)
The signal for osc32k input bypass (Note: in the RTC power domain)
System Boot Mode Select—The operational system boot mode of the i.MX27/MX27L processor
upon system reset is determined by the settings of these pins. BOOT[1:0] are also used as
handshake signals to PMIC(VSTBY).
JTAG Controller select signal—JTAG_CTRL is sampled during rising edge of TRST. Must be
pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal
test purposes only.
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence JTAG test controller’s state machine. Sampled on rising edge of
TCK.
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is
multiplexed with 1-Wire; thus, utilizing 1-Wire will render RTCK unusable and vice versa; PE16.
SD Command bidirectional signal—If the system designer does not want to make use of the
internal pull-up, via the Pull-up enable register, a 4. 7K–69 K external pull up resistor must be
added. This signal is multiplexed with CSPI3_MOSI; PE22.
SD Output Clock. This signal is multiplexed with CSPI3_SCLK; PE23.
SD Data bidirectional signals—If the system designer does not want to make use of the internal
pull-up, via the Pull-up enable register, a 50 K–69 K external pull up resistor must be added.
SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO PE21–18.
SD Command bidirectional signal. This signal is multiplexed with MSHC_BS; through GPIO
multiplexed with SLCDC1_CS; PB8.
SD Output Clock signal. This signal is multiplexed with MSHC_SCLK, through GPIO
multiplexed with SLCDC1_CLK; PB9.
SD Data bidirectional signals. SD2_D[3:0] multiplexed with MSHC_DATA[0:3], also through
GPIO SD2_1:0] multiplexed with SLCDC1_RS and SLDCD1_D0; PB7–PB4.
SD Command bidirectional signal. This signal is multiplexed with ETMTRACEPKT15 and also
through GPIO PD1 multiplexed with FEC_TXD0.
SD Output Clock signal. This signal is through GPIO PD0 multiplexed with FEC_TXD1.
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Secure Digital Interface (X2)
Bootstrap
JTAG
Function/Notes
Signal Descriptions
29