MCIMX27MJP4A Freescale, MCIMX27MJP4A Datasheet - Page 51

• Manufacturer Part Number: MCIMX27MJP4A
• Manufacturer: Freescale

Specifications of MCIMX27MJP4A

• Lead Free Status / RoHS Status: Compliant

HCLK = AHB System Clock, THCLK = Period for HCLK, Tp = Period of CSI_PIXCLK
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold
time and setup time based on the following assumptions:
Rising-edge latch data:
In most of case, duty cycle is 50/50, therefore:
For example: Given pixel clock period = 10 ns, duty cycle = 50/50, hold time = 1 ns, setup time = 1 ns.
Falling-edge latch data:
4.2.5.2
In non-gated mode only, the VSYNC, and PIXCLK signals are used; the HSYNC signal is ignored. Figure
3 and Figure 4 show the different clock edge timing of CSI and Sensor in Non-Gated Mode. Table 3 is the
parameter value.
lists the timing parameters.
Freescale Semiconductor
max rise time allowed = (positive duty cycle
max fall time allowed = (negative duty cycle
max rise time = (period/2
max fall time = (period/2
positive duty cycle = 10/2 = 5 ns
max rise time allowed = 5 –1 = 4 ns
negative duty cycle = 10/2 = 5 ns
max fall time allowed = 5 –1 = 4 ns
max fall time allowed = (negative duty cycle
max rise time allowed = (positive duty cycle
Number
Non-Gated Clock Mode Timing
1
2
3
4
5
6
7
Figure 11
csi_vsync to csi_hsync
csi_hsync to csi_pixclk
csi_d setup time
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
and
Table 21. Gated Clock Mode Timing Parameters
Figure 12
—
Parameter
—
setup time)
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
hold time)
show the non-gated clock mode timings of CSI, and
—
—
—
—
hold time)
setup time)
setup time)
hold time)
Minimum
9*T
T
T
HCLK
HCLK
HCLK
3
1
1
0
Maximum
(Tp/2)-3
HCLK/2
—
—
—
—
—
Electrical Characteristics
MHz
Unit
ns
ns
ns
ns
ns
ns
Table 22
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