MCIMX27LMOP4A Freescale, MCIMX27LMOP4A Datasheet - Page 5

• Manufacturer Part Number: MCIMX27LMOP4A
• Manufacturer: Freescale

Specifications of MCIMX27LMOP4A

• Lead Free Status / RoHS Status: Compliant

The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other
application-specific hardware acceleration to be added. The ARM926EJ-S processor implements ARM
architecture version 5TEJ.
The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports
of the MAX, are designed to support connections to multiple AHB masters external to the platform. An
external arbitration AHB control module is needed if multiple external masters are desired to share an
ARM926 Platform alternate bus master port. However, the alternate bus master ports on the platform
support seamless connection to a single master with no external interface logic required.
A primary AHB MUX (PAHBMUX) module performs address decoding, read data muxing, bus
watchdog, and other miscellaneous functions for the primary AHB within the platform. A clock control
module (CLKCTL) is provided to support a power-conscious design methodology, as well as
implementation of several clock synchronization circuits.
2.1.1
The ARM926EJ-S complex includes 16-Kbyte Instruction and 16-Kbyte Data caches. The embedded
45-Kbyte SRAM (VRAM) can be used to avoid external memory accesses or it can be used for
applications. There is also a 24-Kbyte ROM for bootstrap code.
2.2
Table 2
processors. A cross-reference to each module’s section and page number goes directly to a more detailed
module description for additional information.
Freescale Semiconductor
Block Mnemonic
ARM926EJS
•
•
1-Wire
AITC
AIPI
Separate instruction and data AMBA AHB bus interfaces
ETM and JTAG-based debug support
shows an alphabetical listing of the modules in the i.MX27/MX27L multimedia applications
®
Module Inventory
Memory System
1-Wire Interface
ARM926EJ-S
Block Name
AHB-Lite IP
ARM9EJ-S
Controller
Interface
Interrupt
Module
Connectivity
Bus Control
Bus Control
Functional
Grouping
Peripheral
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Table 2. Digital and Analog Modules
CPU
The 1-Wire module provides bi-directional communication
between the ARM926EJ-S and the Add-Only-Memory EPROM
(DS2502). The 1-Kbit EPROM is used to hold information
about battery and communicates with the ARM926 Platform
using the IP interface.
The AIPI acts as an interface between the ARM Advanced
High-performance Bus Lite. (AHB-Lite) and lower bandwidth
peripherals that conforms to the IP Bus specification, Rev 2.0.
AITC is connected to the primary AHB as a slave device. It
generates the normal and fast interrupts to the ARM926EJ-S
processor.
The ARM926EJ-S (ARM926) is a member of the ARM9 family
of general-purpose microprocessors targeted at multi-tasking
applications.
Brief Description
Functional Description and Application Information
Section/
2.3.2/10
2.3.3/10
2.3.4/10
2.3.1/9
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