MCIMX27LMOP4A Freescale, MCIMX27LMOP4A Datasheet - Page 90

• Manufacturer Part Number: MCIMX27LMOP4A
• Manufacturer: Freescale

Specifications of MCIMX27LMOP4A

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
4.3.11.4
Figure 51
parameters.
90
and
SSI Receiver Timing with External Clock
Figure 52
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when the SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will
be same as that of Tx Data, for example, during the AC97 mode of
operation.
AD1_TXFS (bl)
AD1_TXFS (wl)
(Input)
(Input)
AD1_RXD
AD1_TXC
(Input)
(Input)
Figure 51. SSI Receiver with External Clock Timing Diagram
show the SSI receiver timing with external clock, and
SS23
SS28
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
SS22
SS32
SS35
SS30
NOTE
SS40
SS26
SS25
SS41
SS24
SS36
Table 49
Freescale Semiconductor
SS34
lists the timing