FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet - Page 27

• Manufacturer Part Number: FDC37C78-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C78-HT

• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases.
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must be
very responsive to the service request. This is the
desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in more
frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the
Host
The IRQ pin and RQM bits in the Main Status
Register are activated when the FIFO contains
(16-<threshold>) bytes or the last bytes of a full
sector have been placed in the FIFO. The IRQ pin
can be used for interrupt-driven systems, and
RQM can be used for polled systems. The host
must respond to the request by reading data from
the FIFO. This process is repeated until the last
byte is transferred out of the FIFO. The FDC will
deactivate the IRQ pin and RQM bit when the
FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the
FIFO
The IRQ pin and RQM bit in the Main Status
Register are activated upon entering the execution
phase of data transfer commands. The host must
respond to the request by writing data into the
FIFO. The IRQ pin and RQM bit remain true until
the FIFO becomes full. They are set true again
when the FIFO has <threshold> bytes remaining in
the FIFO. The IRQ pin will also be deactivated if
TC and nDACK both go inactive.
enters the result phase after the last byte is taken
by the FDC from the FIFO (i.e. FIFO empty
condition).
The host reads (writes)
The FDC
27
DMA Mode - Transfers from the FIFO to the Host
The FDC activates the DDRQ pin when the FIFO
contains (16 - <threshold>) bytes, or the last byte
of a full sector transfer has been placed in the
FIFO. The DMA controller must respond to the
request by reading data from the FIFO. The FDC
will deactivate the DDRQ pin when the FIFO
becomes empty. DRQ goes inactive after nDACK
(or on the active edge of nIOR, on the last byte, if
no edge is present on nDACK). A data underrun
may occur if DRQ is not removed in time to
prevent an unwanted cycle.
DMA Mode - Transfers from the Host to the FIFO
The FDC activates the DRQ pin when entering the
execution phase of the data transfer commands.
The DMA controller must respond by activating the
nDACK and nIOW pins and placing data in the
FIFO.
becomes full. DRQ is again set true when the
FIFO has <threshold> bytes remaining in the
FIFO. The FDC will also deactivate the DRQ pin
when TC becomes true (qualified by nDACK),
indicating that no more data is required. DRQ
goes inactive after nDACK goes active for the
last byte of a data transfer (or on the active edge
of nIOW of the last byte, if no edge is present on
nDACK). A data overrun may occur if DRQ is not
removed in time to prevent an unwanted cycle.
Data Transfer Termination
The FDC supports terminal count explicitly through
the
underrun/overrun
functions.
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
goes active for the last byte of a data transfer
TC
DRQ remains active until the FIFO
pin
For full sector transfers, the EOT
and
and
implicitly
end-of-track
through
(EOT)
the