FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet - Page 28

• Manufacturer Part Number: FDC37C78-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C78-HT

• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to complete
the sector as if a hardware TC was received. The
only difference between these implicit functions
and TC is that they return "abnormal termination"
result status.
ignored if they were expected.
Note that when the host is sending data to the
FIFO of the FDC, the internal sector count will be
complete when the FDC reads the last byte from
its side of the FIFO. There may be a delay in the
removal of the transfer request signal of up to the
time taken for the FDC to read the last 16 bytes
from the FIFO. The host must tolerate this delay.
Such status indications can be
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Result Phase
The generation of IRQ determines the beginning
of the result phase. For each of the commands, a
defined set of result bytes has to be read from the
FDC before the result phase is complete. These
bytes of data must be read out for another
command to start.
RQM and DIO must both equal "1" before the
result bytes may be read. After all the result bytes
have been read, the RQM and DIO bits switch to
"1" and "0" respectively, and the CB bit is cleared,
indicating that the FDC is ready to accept the next
command.