IP-POSPHY/P2 Altera, IP-POSPHY/P2 Datasheet - Page 10

• Manufacturer Part Number: IP-POSPHY/P2
• Manufacturer: Altera

Specifications of IP-POSPHY/P2

• Lead Free Status / RoHS Status: Not Compliant

1–6
POS-PHY Level 2 and 3 Compiler User Guide
Table 1–5. Performance—POS-PHY Level 2 PHY Layer—Cyclone II Device (Part 2 of 2)
Table 1–6. Performance—POS-PHY Level 2 PHY Layer—Stratix III Device
Table 1–7. Performance—POS-PHY Level 3 Link Layer—Cyclone III Device
Table 1–8. Performance—POS-PHY Level 3 Link Layer—Stratix III Device
Table 1–9. Performance—POS-PHY Level 3 Link Layer—Stratix IV Device
SPHY transmit
Device: EP2C15AF484C6
MPHY 4-port receive
MPHY 4-port transmit
SPHY receive
SPHY transmit
MPHY 4-port receive
MPHY 4-port transmit
SPHY receive
SPHY transmit
MPHY 4-port receive
MPHY 4-port transmit
SPHY receive
SPHY transmit
MPHY 4-port receive
MPHY 4-port transmit
SPHY receive
SPHY transmit
MPHY 4-port receive
MPHY 4-port transmit
MegaCore Function
MegaCore Function
MegaCore Function
MegaCore Function
MegaCore Function
Preliminary
ALUTs
ALUTs
ALUTs
1,175
1,126
1,202
1,242
149
164
522
613
149
164
522
613
122
123
487
529
285
LEs
LEs
379
377
Registers
Registers
Registers
Logic
Logic
1,019
1,009
Logic
1,019
1,009
309
234
995
918
330
313
330
313
Memory Blocks
Memory Blocks
M4K
M9K
2
8
8
2
2
8
8
Memory Blocks
Memory Blocks
Memory Blocks
© November 2009 Altera Corporation
Performance and Resource Utilization
M9K
M9K
M9K
Chapter 1: About This Compiler
2
2
8
8
2
2
8
8
2
2
8
8
f
f
MAX
MAX
f
f
f
MAX
MAX
MAX
159
161
139
165
139
171
164
(MHz)
(MHz)
340
346
318
293
234
205
217
178
231
180
254
174
(MHz)
(MHz)
(MHz)