IP-POSPHY/P2 Altera, IP-POSPHY/P2 Datasheet - Page 35

• Manufacturer Part Number: IP-POSPHY/P2
• Manufacturer: Altera

Specifications of IP-POSPHY/P2

• Lead Free Status / RoHS Status: Not Compliant

Chapter 3: Functional Description
Parameters
Parameters
Interface Settings
© November 2009 Altera Corporation
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For more information on OpenCore Plus hardware evaluation, see
Evaluation” on page 1–4
The function’s parameters, which can only be set in IP Toolbench (see
Parameterize” on page
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FIFO Buffer & Clock Selector Options
The following interface ‘B’ FIFO buffer and clock selector options are available:
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For the POS-PHY receive interface:
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For the POS-PHY transmit interface:
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Interface Settings
Parity Settings
FIFO Buffer Settings
Address & Packet Available Settings
A Clock (No FIFO buffer)—only available if the ‘B’ interface is an Atlantic master,
and the ‘B’ interface bus width ≥ the ‘A’ interface bus width. The relevant ‘B’
interface does not use an internal FIFO buffer, and is clocked by the ‘A’ interface
clock pin. This is recommended only if you connect ‘B’ interfaces directly to
another MegaCore function with an Atlantic slave interface
A Clock—the corresponding ‘B’ interface uses an internal single clock FIFO buffer,
and is clocked by the A interface clock pin
The sop_ina input goes low
The addr_outa output goes low
The dpav_outa output goes low
The ppav_outa output goes low
The spav_outa output goes low
The rd_outa output goes low
The wr_outA output goes low
The val_outA output goes low
'The sx_outA output goes low
The sop_outA output goes low
'The eop_outA output goes low
The err_outA output goes high
The data_outA output goes low
2–5), include the following settings:
and
Preliminary
AN 320: OpenCore Plus Evaluation of
POS-PHY Level 2 and 3 Compiler User Guide
Megafunctions.
“OpenCore Plus
“Step 1:
3–7