AD73322LYRUZ Analog Devices Inc, AD73322LYRUZ Datasheet
AD73322LYRUZ
Specifications of AD73322LYRUZ
Related parts for AD73322LYRUZ
AD73322LYRUZ Summary of contents
Page 1
GENERAL DESCRIPTION The AD73322L is a dual front-end processor for general pur- pose applications including speech and telephony. It features two 16-bit A/D conversion channels and two 16-bit D/A con- version channels. Each channel provides 78 dB signal-to-noise ratio ...
Page 2
AD73322L–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance INPUT AMPLIFIER Offset Maximum Output Swing Feedback Resistance Feedback Capacitance ANALOG GAIN TAP Gain at Maximum Setting ...
Page 3
Parameter DAC SPECIFICATIONS 2 Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing (0 dBm0) Single-Ended Differential Output Bias Voltage Absolute Gain Gain Tracking Error Signal to (Noise + Distortion dBm0 PGA = 0 dB Total Harmonic ...
Page 4
AD73322L Parameter LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUT V , Output High Voltage Output Low Voltage OL ...
Page 5
VREFCAP VREFOUT ADC DAC TIMING CHARACTERISTICS Limit at Parameter T = – +105 C A Clock Signals 24 24.4 3 Serial Port 0.4 × ...
Page 6
AD73322L MCLK SCLK* SE (I) THREE- SCLK (O) STATE SDIFS (I) SDI (I) t THREE- 9 SDOFS (O) STATE THREE- STATE SDO ( ...
Page 7
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted) A AVDD, DVDD to GND . . . . . . . . . . . . . . . –0 +4.6 V AGND to DGND . . . ...
Page 8
AD73322L Mnemonic Function VINP1 Analog Input to the inverting input amplifier on Channel 1’s positive input. VFBP1 Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input amplifiers are bypassed, this pin allows ...
Page 9
TERMINOLOGY Absolute Gain Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at ...
Page 10
AD73322L –Typical Performance Characteristics –10 –85 –75 –65 –55 –45 –35 V – dBm0 IN VFBN1 VINN1 ANALOG V LOOP REF BACK VINP1 VFBP1 VOUTP1 CONTINUOUS +6/15dB LOW-PASS PGA VOUTN1 REFCAP ...
Page 11
FUNCTIONAL DESCRIPTION Encoder Channels Both encoder channels consist of a pair of inverting op amps with feedback connections that can be bypassed if required, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms ...
Page 12
AD73322L F = 4kHz B SIGNAL TRANSFER FUNCTION NOISE TRANSFER FUNCTION F = 4kHz 4kHz F = DMCLK/256 B SINTER F = 4kHz F = 8kHz F B SFINAL SINTER Decimation Filter The digital filter used in ...
Page 13
Interpolation Filter The anti-imaging interpolation filter is a sinc-cubed digital filter that up-samples the 16-bit input words from the input sample rate to a rate of DMCLK/8, while filtering to attenuate images produced by the interpolation process. Its Z transform ...
Page 14
AD73322L MCLK EXTERNAL DMCLK INTERNAL MCLK DIVIDER 3 SE SERIAL PORT 1 RESET (SPORT 1) SDIFS SDI SERIAL REGISTER CONTROL CONTROL CONTROL REGISTER REGISTER REGISTER CONTROL CONTROL REGISTER REGISTER 1G CONTROL REGISTER ...
Page 15
In both transmit and receive modes, data is transferred at the serial clock (SCLK) rate with the MSB being transferred first. Due to the fact that the SPORT of each codec block uses a com- mon serial register for serial ...
Page 16
AD73322L Serial Clock Rate Divider The AD73322L features a programmable serial clock divider that allows users to match the serial clock (SCLK) rate of the data to that of the DSP engine or host processor. The maximum SCLK rate available ...
Page 17
Address (Binary) Name 000 CRA 001 CRB 010 CRC 011 CRD 100 CRE 101 CRF 110 CRG 111 CRH C/D R/W Device Address Control Frame Bit 15 Control/Data Bit 14 Read/Write Bits 13–11 Device Address ...
Page 18
AD73322L CONTROL REGISTER Bit CONTROL REGISTER B 7 — Bit CONTROL REGISTER Bit 0 ...
Page 19
CONTROL REGISTER D 7 MUTE Bit CONTROL REGISTER E 7 — Bit CONTROL REGISTER F 7 ALB/ AGTM Bit ...
Page 20
AD73322L CONTROL REGISTER G 7 DGTC7 Bit CONTROL REGISTER H 7 DGTC15 DGTC14 DGTC13 DGTC12 DGTC11 DGTC10 DGTC9 Bit Table XIX. Control Register G ...
Page 21
OPERATION Resetting the AD73322L The RESET pin resets all the control registers. All registers are reset to zero, indicating that the default SCLK rate (DMCLK/ 8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP ...
Page 22
AD73322L In a single AD73322L configuration, each 16-bit data frame sent from the DSP to the device is interpreted as DAC data, but it is necessary to send two DAC words per sample period in order to ensure DAC update. ...
Page 23
INTERFACING The AD73322L can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompa- nying frame synchronization signal that is active high one ...
Page 24
AD73322L Table XXI. Device Count Settings DC2 DC1 DC0 PERFORMANCE As the AD73322L is designed to ...
Page 25
The device features an on-chip master clock divider circuit that allows the sample rate to be reduced as the sampling rate of the sigma-delta converter is proportional to the output of the MCLK Divider (whose default state is divide-by-one). The ...
Page 26
AD73322L As the AD73322L can be operated at 8 kHz (see Figure 22 kHz sampling rates, which make it particularly suited for voice- band processing important to understand the action of the interpolator’s Sinc3 response. As ...
Page 27
DESIGN CONSIDERATIONS The AD73322L features both differential inputs and outputs on each channel to provide optimal performance and avoid com- mon mode noise also possible to interface either inputs or outputs in single-ended mode. This section details the ...
Page 28
AD73322L 100pF 50k VFBN1 50k VINN1 V REF 50k VINP1 50k VFBP1 GAIN 100pF VOUTP1 +6/–15dB PGA VOUTN1 REFOUT REFERENCE REFCAP 0 the case of ac coupling, a capacitor is used to couple the signal to the input ...
Page 29
VFBN1 VINN1 B V REF ELECTRET PROBE VINP1 VFBP1 GAIN 1 VOUTP1 +6/–15dB PGA VOUTN1 REFOUT REFCAP C REFCAP Analog Output The AD73322L’s differential analog output (VOUT) is produced by ...
Page 30
AD73322L SDIFS TFS DT SCLK SCLK ADSP-218x DR SDO DSP RFS SDOFS RESET FL0 FL1 SDIFS FSX DT CLKX SCLK CLKR TMS320C5x DSP DR FSR SDOFS RESET XF Cascade Operation Where it is required to configure a cascade of up ...
Page 31
The printed circuit board that houses the AD73322L should be designed so the analog and digital sections are separated and confined to certain sections of the board. The AD73322L pin configuration offers a major advantage in that its analog and ...
Page 32
AD73322L Mixed-Mode Operation To take full advantage of mixed-mode operation necessary to configure the DSP/Codec interface in NonFSLB and to disable autobuffering. This allows a variable numbers of words to be sent to the AD73322L in each sample ...
Page 33
DSP program initializes pointers to the top of the buffer i3 = ^init_cmds %init_cmds; and puts the first entry in the DSP’s transmit buffer so that it is available at the first SDOFS pulse. ax0 = ...
Page 34
AD73322L APPENDIX A DAC Timing Control Example The AD73322L’s DAC is loaded from the DAC register con- tents just before the ADC register contents are loaded to the serial register (SDOFS going high). This default DAC load position can be ...
Page 35
APPENDIX B Configuring an AD73322L to Operate in Data Mode This section describes the typical sequence of control words that are required to be sent to an AD73322L to set it up for data mode operation. In this sequence Registers ...
Page 36
AD73322L DSP Step Tx 1 CRB–CH2 1000100100001011 2 CRB–CH1 1000000100001011 3 CRC–CH2 1000101011111001 4 CRC–CH2 1000101011111001 5 CRC–CH1 1000001011111001 6 CRA–CH2 1000100000010001 7 CRA–CH2 1000100000010001 8 CRA–CH1 1000000000010001 9 CRB-CH2 0111111111111111 10 DAC WORD CH 2 0111111111111111 11 DAC WORD ...
Page 37
APPENDIX C Configuring an AD73322L to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to an AD73322L to configure it for operation in mixed mode not intended to be ...
Page 38
AD73322L DSP Step Tx DON’T CARE 1 xxxxxxxxxxxxxxxx DON’T CARE 2 xxxxxxxxxxxxxxxx CRA-CH2 3 1000101011111001 CRA-CH1 4 1000000000010011 DON’T CARE 5 xxxxxxxxxxxxxxxx DON’T CARE 6 xxxxxxxxxxxxxxxx DON’T CARE 7 xxxxxxxxxxxxxxxx CRB-CH2 8 1000100100001011 CRB-CH1 9 1000000100001011 DON’T CARE 10 xxxxxxxxxxxxxxxx ...
Page 39
Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
Page 40
AD73322L 0.0118 (0.30) 0.0040 (0.10) PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.030 (0.75) 0.019 (0.50) SEATING 0.004 (0.10) 0.006 (0.15) 0.002 (0.05) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Wide Body SOIC (R-28) 0.7125 (18.10) 0.6969 ...