MIC74BQS Micrel Inc, MIC74BQS Datasheet - Page 5

• Manufacturer Part Number: MIC74BQS
• Description: IC I/O EXPANDER I2C 8B 16QSOP
• Manufacturer: Micrel Inc
• Series: -r

Specifications of MIC74BQS

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: -
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.154", 3.90mm Width)
• Includes: -
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Register Descriptions
Device Configuration Register
Power-On Default Value: 0000 0000
Command_byte addess: 0000 0000
Type:
Bit Name: IE
Function:
Operation: 1 = enabled
Bit Name: FAN
Function:
Operation: 1 = Fan Mode
Bit Name: D[2] through D[6]
Function:
Operation: Reserved—always write as zero
Data Direction Register
Power-On Default Value: 0000 0000
Command_byte addess: 0000 0001
Type:
Bit Name: DIRn
Function:
Operation: 1 = output
Notes:
Micrel, Inc.
October 2006
DIR7
D[7]
D[7]
DIR6
D[6]
D[6]
Always write as zero
Interrupts disabled
Not in Fan Mode
8-bits, read/write
Global interrupt enable
0 = disabled
Selects Fan Mode
(P[7:4] vs. /FS[2:0], /SHDN)
0 = I/O Mode
Reserved
all Pn’s configured as inputs
8-bits, read/write
Selects data direction, input or output, of Pn
0 = input
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. The DIR register has no effect on
these I/O bits while in Fan Mode.
DIR5
D[5]
D[5]
D[4]
DIR4
D[4]
DEV_CFG
DIR
D[3]
DIR3
D[3]
b
b
b
b
D[2]
, 00
DIR2
, 01
D[2]
, 00
, 00
h
h
h
h
FAN
D[1]
DIR1
D[1]
D[0]
DIR0
D[0]
IE
5
Output Configuration Register
Power-On Default Value: 0000 0000
Command_byte addess: 0000 0010
Type:
Bit Name: OUTn
Function:
Operation: 1 = push-pull
Notes:
Status Register
Power-On Default Value: 0000 0000
Command_byte addess: 0000 0011
Type:
Bit Name: Sn
Function:
Operation: 1 = change occurred
Notes:
OUT7
D[7]
D[7]
S7
D[6]
OUT6
S6
D[6]
all outputs open-drain
8-bits, read/write
Selects output driver configuration of Pn when
Pn is configured as an output.
0 = open-drain
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. The OUT_CFG register has no effect
on these I/O bits while in Fan Mode.
no interrupts pending
8-bits, read only
Flag for Pn input-change event when Pn is
configured as an input; Sn is set when the
corresponding input changes state.
0 = no change occurred
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. No interrupts of any kind are
generated by these pins while in Fan Mode.
All status bits are cleared after any read
operation is performed on STATUS.
D[5]
S5
OUT5
D[5]
D[4]
S4
STATUS
OUT4
D[4]
OUT_CFG
D[3]
S3
OUT3
D[3]
b
b
b
b
, 02
, 03
D[2]
, 00
, 00
S2
h
h
OUT2
h
h
D[2]
D[1]
M9999-101006
S1
OUT1
D[1]
MIC74
D[0]
S0
OUT0
D[0]