ICS9FG1201HFLF IDT, Integrated Device Technology Inc, ICS9FG1201HFLF Datasheet - Page 4

• Manufacturer Part Number: ICS9FG1201HFLF
• Description: IC FREQUENCY GENERATOR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG1201HFLF

• Input: Clock
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9FG1201HFLF

Pin Description (continued)
IDT
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pin # Pin Name
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
TM
/ICS
SMBCLK
SMB_A2_PLLBYP#
OE6#
DIF_6#
DIF_6
OE7#
DIF_7#
DIF_7
GND
VDD
DIF_8#
DIF_8
OE8#
DIF_9#
DIF_9
OE9#
VTT_PWRGD#/PD
FS_A_410
DIF_10#
DIF_10
GND
VDD
DIF_11#
DIF_11
OE10_11#
IREF
GNDA
VDDA
TM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Type
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
Pin Description
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit 2. When Low, the part operates as a fanout buffer
with the PLL bypassed. When High, the part operates as a zero-delay
buffer (ZDB) with the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling output pairs 10 and 11.
1 = tri-state outputs, 0 = enable outputs
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
3.3V tolerant low threshold input for CPU frequency selection. This
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1371F — 09/23/09