ICS9FG1201HFLF IDT, Integrated Device Technology Inc, ICS9FG1201HFLF Datasheet - Page 8

• Manufacturer Part Number: ICS9FG1201HFLF
• Description: IC FREQUENCY GENERATOR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG1201HFLF

• Input: Clock
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9FG1201HFLF

* Note: See SMBus Address Mapping (page 7), for programming SMBus Read/Write Address
IDT
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
TM
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D0
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
/ICS
Byte N + X -1
WR
P
T
TM
Beginning Byte N
Data Byte Count = X
Index Block Write Operation
Slave Address D0
Beginning Byte = N
Byte N + X - 1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Controller (Host)
General SMBus serial interface information for the ICS9FG1201H
starT bit
stoP bit
WRite
(h)
*
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
(h)
8
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D0
• ICS clock will acknowledge
• Controller (host) sends the begining byte
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D1
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
location = N
was written to byte 8)
WR
RD
RT
N
P
T
Slave Address D0
Slave Address D1
Index Block Read Operation
Beginning Byte = N
Controller (Host)
Not acknowledge
ACK
ACK
Repeat starT
starT bit
stoP bit
WRite
ReaD
(h)
(h)
*
*
.
ICS (Slave/Receiver)
Data Byte Count = X
Beginning Byte N
Byte N + X - 1
ACK
ACK
ACK
1371F — 09/23/09
(h)
(h)
(h)