ICS9FG1201HFLF IDT, Integrated Device Technology Inc, ICS9FG1201HFLF Datasheet
ICS9FG1201HFLF
Specifications of ICS9FG1201HFLF
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ICS9FG1201HFLF Summary of contents
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Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Description The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Pin Configuration Functionality Table CLK_IN (CPU FSB) 1 FS_A_410 MHz 1 100.00 1 133.33 1 166. 200.00 0 266.66 0 333.33 0 400.00 1. FS_A_410 is a ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Power Groups Pin Number VDD GND 56 55 Main PLL, Analog 11,22,38,50 12,23,37,49 Pin Description Pin # Pin Name 1 HIGH_BW# 2 CLK_IN 3 CLK_IN# 4 SMB_A0 5 OE0# ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Pin Description (continued) Pin # Pin Name 29 SMBCLK 30 SMB_A2_PLLBYP# 31 OE6# 32 DIF_6# 33 DIF_6 34 OE7# 35 DIF_7# 36 DIF_7 37 GND 38 VDD 39 DIF_8# ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD ICS9FG1201 Programmable Gear Ratios SMBus Byte 0 Input Output (m) ( ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD ICS 9FG1201H 1:1 PLL Programming Byte 8, Byte 8, Byte 8, bit 2 bit 1 bit 0 FSC FSB FS_A_410 ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD TM TM IDT /ICS 9FG1201/2 SMBus Address Mapping when using CK410B+ and DB400/800 SMB_A(2:0) = 000 SMB Adr: D0 ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD General SMBus serial interface information for the ICS9FG1201H How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D0 • ICS clock ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD SMBusTable: Gear Ratio Select Register Byte 0 Pin # Name Bit 7 DIF(9:0) Group of 10 gear ratio enable Bit 6 DIF(11:10) Group of 2 gear ratio enable - ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD SMBusTable: Output Enable Readback Register Byte 4 Pin # Name Bit 7 46 Bit 6 1 Readback - HIGH_BW Readback - SMB_A2_PLLBYP# In Bit 5 Bit 4 ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD SMBusTable: 1:1 PLL Frequency Selection Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 - Bit 2 - Bit 1 - Bit 0 ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD SMBus Table: Gear PLL Frequency Control Register Byte 12 Pin # Name - Gear PLL N Div7 Bit 7 - Gear PLL N Div6 Bit 6 - Gear PLL ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD SMBusTable: Reserved Register Byte 16 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: 1:1 PLL Frequency ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD SMBusTable: Reserved Register Byte 20 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Test Byte Register Byte ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Absolute Max PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Supply Voltage VDD_In Storage Temperature Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection ESD prot Electrical ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Electrical Characteristics - DIF 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Zo ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Electrical Characteristics - Skew and Differential Jitter Parameters 70°C; Supply Voltage V = 3.3 V +/- Group Parameter t CLK_IN, DIF[x:0] SPO_PLL CLK_IN, ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Electrical Characteristics - Phase Jitter PARAMETER SYMBOL t jphPCIe1 t jphPCIe2Lo Jitter, Phase t jphPCIe2Hi t jphFBD1_3.2G t jphFBD1_4.8G Notes on Phase Jitter: 1 See http://www.pcisig.com for complete specs. ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Alternative termination for LVDS and other common differential signals. Vdiff Vp-p Vcm 0.45 v 0.22v 1.08 0.58 0.6 0.28 0.80 0.40 0.6 0.60 1.2 0.3 R1a = R1b = ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD INDEX INDEX AREA AREA 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C Frequency Gearing ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD INDEX INDEX AREA AREA Ordering Information Part / Order Number Shipping/Packaging 9FG1201HGLF 9FG1201HGLFT Tape and Reel ...
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ICS9FG1201H Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD Revision History Rev. Issue Date Description A 10/22/2007 Release to Final. Updated Key Specifications: B 1/29/2008 Changed units for DIF output-to-output skew to "ps". C 2/12/2008 Changed Cin value ...