ICS954119DFLF IDT, Integrated Device Technology Inc, ICS954119DFLF Datasheet - Page 12

• Manufacturer Part Number: ICS954119DFLF
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS954119DFLF

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 954119DFLF

0875—05/24/04
1
1
2
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Absolute Maximum Rating
Electrical Characteristics - Input/Supply/Common Output Parameters
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
Input ESD protection HBM
3.3V Core Supply Voltage
Operating Supply Current
Ambient Operating Temp
Low-level Output Voltage
3.3V Logic Input Supply
Modulation Frequency
Clock/Data Rise Time
Storage Temperature
Low Threshold Input-
Low Threshold Input-
Clock/Data Fall Time
Powerdown Current
Case Temperature
Input High Current
Input High Voltage
Input Low Current
Operating Current
Input Capacitance
Input Low Voltage
Current sinking at
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
PARAMETER
PARAMETER
SCLK/SDATA
SCLK/SDATA
High Voltage
Low Voltage
Tdrive_PD#
V
Integrated
Circuit
Systems, Inc.
Trise_Pd#
Tfall_Pd#
OL
Voltage
= 0.4 V
SYMBOL
Tambient
SYMBOL
ESD prot
VDD_In
VDD_A
I
I
I
Tcase
V
V
I
DD3.3OP
DD3.3OP
DD3.3PD
T
PULLUP
C
T
T
C
IH_FSL
IL_FSL
L
C
V
V
Ts
V
V
I
I
STAB
I
F
IL1
IL2
RI2C
FI2C
OUT
IH
pin
INX
DD
OL
IH
IL
IN
i
V
assertion of PD# to 1st clock
IN
V
all differential pairs tri-stated
From V
Full Active, C
IN
= 0 V; Inputs with no pull-up
CPU output enable after
Output pin capacitance
Triangular Modulation
= 0 V; Inputs with pull-up
(Max VIL - 0.15) to
(Min VIH + 0.15) to
all diff pairs driven
PD# de-assertion
all outputs driven
(Min VIH + 0.15)
(Max VIL - 0.15)
PD# rise time of
CONDITIONS*
PD# fall time of
CONDITIONS
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
DD
V
V
resistors
@ I
resistors
DD
Power-Up or de-
IN
= 3.3 V
= V
PULLUP
-
-
-
-
-
-
L
= Full load;
DD
12
GND - 0.5
V
V
SS
SS
2000
-200
MIN
MIN
-65
0.7
2.7
30
-5
-5
0
2
4
- 0.3
- 0.3
14.31818
TYP
TYP
Advance Information
V
V
V
V
DD
DD
DD
DD
MAX
MAX
1000
0.35
150
115
350
400
300
300
0.8
1.8
5.5
0.4
+ 0.5V
+ 0.5V
70
70
12
33
+ 0.3
5
+ 0.3
7
5
6
5
5
5
UNITS
UNITS
ICS954119
MHz
kHz
mA
mA
mA
mA
ms
mA
uA
uA
uA
nH
pF
pF
pF
°
°C
°C
us
ns
ns
ns
ns
V
V
V
V
V
V
V
C
V
V
Notes
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1