ICS954119DFLF IDT, Integrated Device Technology Inc, ICS954119DFLF Datasheet - Page 9

• Manufacturer Part Number: ICS954119DFLF
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS954119DFLF

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 954119DFLF

0875—05/24/04
I
I
I
I
I
2
2
2
2
2
C Table: M/N Programming & WD Safe Frequency Control Register
C Table: PLL1 Frequency Control Register
C Table: PLL1 Frequency Control Register
C Table: PLL1 Spread Spectrum Control Register
C Table: PLL1 Spread Spectrum Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 10
Byte 11
Byte 12
Byte 13
Byte 14
Integrated
Circuit
Systems, Inc.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
Pin #
WD Safe Freq Source
Reserved
Reserved
M/N_EN
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Name
Name
N Div8
N Div9
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Name
Name
SSP14
SSP13
SSP12
SSP11
SSP10
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
SSP9
SSP8
M Divider Programming
N Divider Programming
WD Safe Freq Source
Programming bit(14:8)
Watch Dog Safe Freq
Programming Enable
Programming bit(7:0)
Control Function
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
Control Function
Byte12 bit(7:0) and
Control Function
Control Function
Programming bits
Spread Spectrum
Spread Spectrum
Byte11 bit(7:6)
PLL1 M/N
Reserved
Reserved
bit (5:0)
9
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Writing to these bit will configure the safe frequency as Byte0 bit
The decimal representation of M and N Divier in Byte 11 and 12
The decimal representation of M and N Divier in Byte 11 and 12
These Spread Spectrum bits in Byte 13 and 14 will program the
These Spread Spectrum bits in Byte 13 and 14 will program the
will configure the PLL1 VCO frequency. Default at power up =
will configure the PLL1 VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x
latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x
B10b(4:0)
Disable
0
0
0
0
0
-
-
[NDiv(9:0)+8] / [MDiv(5:0)+2]
[NDiv(9:0)+8] / [MDiv(5:0)+2]
spread pecentage of PLL1
spread pecentage of PLL1
Advance Information
(4:0).
Latch Inputs
Enable
1
1
1
1
1
-
-
ICS954119
PWD
PWD
PWD
PWD
PWD
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X