SI5368B-C-GQR Silicon Laboratories Inc, SI5368B-C-GQR Datasheet - Page 16

• Manufacturer Part Number: SI5368B-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register
10
11
12
13
14
15
16
17
18
19
20
21
22
0
1
2
3
4
5
6
7
8
9
Si5368
3. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, such as Register 64, should never be written to.
16
FLAT_VALID
FPW_VALID
ALIGN_POL
INCDEC_
FOS_EN
FSYNC_
AUTOSEL_REG [1:0]
CKSEL_REG [1:0]
PIN
CK_PRIOR4 [1:0]
D7
HLOG_4 [1:0]
ICMOS [1:0]
ALIGN_THR [2:0]
ALIGN_REG
FREE_RUN
FSYNC_
FSYNC_
SLEEP
BWSEL_REG [3:0]
POL
D6
FOS_THR [1:0]
HIST_AVG [4:0]
ALRMOUT_
ALIGN_PIN
ALWAYS_
CKOUT_
FSYNC_
FSYNC_
DSBL5_
DHOLD
ALIGN_
MODE
REG
PIN
ON
CK_PRIOR3 [1:0]
D5
HLOG_3 [1:0]
SFOUT2_REG [2:0]
SFOUT4_REG [2:0]
SFOUT5_REG [2:0]
Preliminary Rev. 0.41
CK4_ACTV_
FSYNCOUT
CK3_BAD_
SQ_ICAL
SWTCH_
FSYNC_
FSYNC_SKEW [15:8]
FSYNC_SKEW [7:0]
_POL
REG
PIN
PIN
D4
FSYNC_PW [7:0]
VALTIME [1:0]
CLAT [7:0]
FLAT [7:0]
CK_CONFIG
CK3_ACTV_
FLAT [14:8]
CK2_BAD_
CK_ACTV_
FSKEW_
PD_CK4
DSBL4_
VALID
_REG
REG
POL
PIN
PIN
CK_PRIOR2 [1:0]
D3
HLOG_2 [1:0]
HIST_DEL [4:0]
CK2_ACTV_
CK1_BAD_
CK_BAD_
PD_CK3
FSYNC_
DSBL3_
[16:16]
SKEW
REG
POL
PIN
PIN
D2
SFOUT1_REG [2:0]
SFOUT3_REG [2:0]
FOSREFSEL [2:0]
CK1_ACTV_
LOCKT [2:0]
BYPASS_
LOL_POL
LOL_PIN
PD_CK2
DSBL2_
REG
REG
PIN
CK_PRIOR1 [1:0]
FSYNC_PW [9:8]
D1
HLOG_1 [1:0]
HLOG_5 [1:0]
CKSEL_PIN
INT_POL
PD_CK1
INT_PIN
DSBL1_
REG
D0