SI5368B-C-GQR Silicon Laboratories Inc, SI5368B-C-GQR Datasheet - Page 9

• Manufacturer Part Number: SI5368B-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Functional Description
The Si5368 is a jitter-attenuating precision clock multiplier
for applications requiring sub 1 ps rms jitter performance.
The Si5368 accepts four clock inputs ranging from 2 kHz
to 710 MHz and generates five clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation
combination across this operating range. Independent
dividers are available for every input clock and output
clock, so the Si5368 can accept input clocks at different
frequencies and it can generate output clocks at different
frequencies. The Si5368 input clock frequency and clock
multiplication ratio are programmable through an I
SPI interface. Optionally, the fifth clock output can be
configured as a 2 to 512 kHz SONET/SDH frame
synchronization output that is phase aligned with one of
the high-speed output clocks. Silicon Laboratories offers a
PC-based software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination that
minimizes phase noise and power consumption. This
utility
http://www.silabs.com/timing
The Si5368 is based on Silicon Laboratories' 3rd-
generation DSPLL
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5368
PLL loop bandwidth is digitally programmable and
supports a range from 60 Hz to 8.4 kHz. The DSPLLsim
software utility can be used to calculate valid loop
bandwidth settings for a given input clock frequency/clock
multiplication ratio.
The Si5368 supports hitless switching between input
clocks in compliance with GR-253-CORE and GR-1244-
CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (<200 ps typ). Manual, automatic revertive and
non-revertive input clock switching options are available.
The Si5368 monitors the four input clocks for loss-of-
signal and provides a LOS alarm when it detects missing
pulses on any of the four input clocks. The device
monitors the lock status of the PLL. The lock detect
algorithm works by continuously monitoring the phase of
the input clock in relation to the phase of the feedback
clock. The Si5368 monitors the frequency of CKIN1,
CKIN2, CKIN3, and CKIN4 with respect to a selected
reference frequency and generates a frequency offset
alarm (FOS) if the threshold is exceeded. This FOS
feature is available for SONET applications in which both
the monitored frequency on CKIN1, CKIN3, and CKIN4
and the reference frequency are integer multiples of 19.44
MHz. Both Stratum 3/3E and SONET Minimum Clock
(SMC) FOS thresholds are supported.
The Si5368 provides a digital hold capability that allows
the device to continue generation of a stable output clock
when the selected input reference is lost. During digital
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hold, the DSPLL generates an output frequency based on
a historical average that existed a fixed amount of time
before the error event occurred, eliminating the effects of
phase and frequency transients that may occur
immediately preceding digital hold.
Fine phase adjustment is available and is set using the
FLAT register bits. The nominal range and resolution of
the FLAT[14:0] latency adjustment word are: ±110 ps and
3 ps, respectively.
The Si5368 has five differential clock outputs. The
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. The phase difference
between the selected input clock and the output clocks is
adjustable in 200 ps increments for system skew control.
In addition, the phase of one output clock may be
adjusted in relation to the phase of the other output clock.
The resolution varies from 800 ps to 2.2 ns depending on
the PLL divider settings. Consult the DSPLLsim
configuration software to determine the phase offset
resolution for a given input clock/clock multiplication ratio
combination. For system-level debugging, a bypass mode
is available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8 or 2.5 V supply.
1.1. External Reference
An external, 38.88 MHz clock or a low-cost 114.285 MHz
3rd overtone crystal is used as part of a fixed-frequency
oscillator within the DSPLL. This external reference is
required for the device to operate. Silicon Laboratories
recommends using a high-quality crystal. Specific
recommendations may be found in the Family Reference
Manual. An external clock from a high-quality OCXO or
TCXO can also be used as a reference for the device.
In digital hold, the DSPLL remains locked to this external
reference. Any changes in the frequency of this reference
when the DSPLL is in digital hold, will be tracked by the
output of the device. Note that crystals can have
temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5368. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
Si5368
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