W40S01-04H Cypress Semiconductor Corp, W40S01-04H Datasheet
W40S01-04H
Specifications of W40S01-04H
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W40S01-04H Summary of contents
Page 1
... DC to 133-MHz operation • Single 3.3V supply voltage • Low power CMOS design packaged in a 48-pin SSOP (Small Shrink Outline Package) Overview The Cypress W40S01- low-voltage, eighteen-output signal buffer. Output buffer impedance is approximately 15 which is ideal for driving SDRAM DIMMs. Block Diagram SDATA ...
Page 2
... SMBus section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane. Output Enable: Internal 250-k pull-up resistor. Three-states outputs when LOW. No Connect: Do not connect. 2 W40S01- ...
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... Data is written to the W40S01-04 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1. Byte Description Commands the W40S01-04 to accept the bits in Data Bytes 0-6 for inter- nal register configuration. Since other devices may exist on the same common serial data bus necessary to have a specific slave address for each potential receiver ...
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... Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 4 W40S01-04 Bit Control 0 1 Low Active Low Active Low Active Low Active Low Active ...
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... Electrical Requirements Figure 1 illustrates electrical characteristics for the serial inter- face bus used with the W40S01-04. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resis- ...
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... A write sequence is initiated by a “start bit” as shown in Figure 3. A “stop bit” signifies that a transmission has ended. As stated previously, the W40S01-04 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 4. SDATA ...
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... Figure 4. Serial Data Bus Write Sequence Figure 5. Serial Data Bus Timing Diagram 7 W40S01-04 ...
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... V = 3.3V ± DDQ3 Test Condition/ Comments BUF_IN = 100 MHz BUF_IN = 100 MHz [ – 1. 1. W40S01-04 Rating Unit –0.5 to +7.0 V –65 to +150 ° +70 °C –55 to +125 °C Min. Typ. Max. Unit 320 5 GND–0.3 0.8 2.0 V +0.5 DDQ3 – ...
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... Capacitance Test Load = 30 pF) A DDQ3 Test Condition Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured at 1.5V Package Name Package Type H 48-pin SSOP (300 mils) 9 W40S01-04 Min. Typ. Max. Unit 0 133 MHz 1.5 4.0 V/ns 1.5 4.0 V/ns ...
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... Layout Example SDATA VIA to GND plane layer +3.3V Supply =VIA to supply plane layer 10 W40S01- SCLOCK ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W40S01-04 ...