ICS85105AGILF IDT, Integrated Device Technology Inc, ICS85105AGILF Datasheet
![IC FANOUT BUFFER HCSL 20-TSSOP](/photos/6/52/65204/ics85105agilf_sml.jpg)
ICS85105AGILF
Specifications of ICS85105AGILF
800-1152-5
800-1152
85105AGILF
Related parts for ICS85105AGILF
ICS85105AGILF Summary of contents
Page 1
Low Skew, 1-to-5, Differential/LVCMOS- to-0.7V HCSL Fanout Buffer G D ENERAL ESCRIPTION The ICS85105I is a low skew, high performance 1-to-5 Differ- ential-to-0.7V HCSL Fanout Buffer. The ICS85105I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most ...
Page 2
ICS85105I Data Sheet ABLE IN ESCRIPTIONS ...
Page 3
ICS85105I Data Sheet ABLE ONTROL NPUT UNCTION ...
Page 4
ICS85105I Data Sheet BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance Lead TSSOP Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...
Page 5
ICS85105I Data Sheet ABLE HARACTERISTICS ...
Page 6
ICS85105I Data Sheet The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and ...
Page 7
ICS85105I Data Sheet P ARAMETER 3.3V±10 HCSL 50 IREF GND 475 0V This load condition is used for sk(o HCSL UTPUT OAD EST IRCUIT V DD nCLK0 ...
Page 8
ICS85105I Data Sheet P ARAMETER Clock Period (Differential) Positive Duty Cycle (Differential) 0. IFFERENTIAL EASUREMENT OINTS FOR T STABLE V RB +150mV V = +100mV RB 0. -100mV RB -150mV Q - ...
Page 9
ICS85105I Data Sheet R U ECOMMENDATIONS FOR NUSED I : NPUTS CLK I NPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection resistor can ...
Page 10
ICS85105I Data Sheet IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both differential signals must meet the V and V input requirements. Figures show PP ...
Page 11
ICS85105I Data Sheet R T ECOMMENDED ERMINATION Figure 4A is the recommended source termination for applications where the driver and receiver will be on separate PCBs. This termination is the standard for PCI Express and 0.5" Max ...
Page 12
ICS85105I Data Sheet This section provides information on power dissipation and junction temperature for the ICS85105I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85105I is the sum of the core power ...
Page 13
ICS85105I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 5. R REF = 475 HCSL ...
Page 14
ICS85105I Data Sheet ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS85105I is: 614 ...
Page 15
ICS85105I Data Sheet ABLE RDERING NFORMATION ...
Page 16
ICS85105I Data Sheet ICS85105AGI REVISION A MAY 27, 2011 LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V ...
Page 17
ICS85105I Data Sheet We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road Sales San Jose, CA 95138 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to ...