ADF4206BRU Analog Devices Inc, ADF4206BRU Datasheet - Page 22

• Manufacturer Part Number: ADF4206BRU
• Description: IC PLL FREQ SYNTHESIZER 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4206BRU

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 550MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 550MHz

ADF4206/ADF4208
INTERFACING
The ADF420x family has a simple SPI®-compatible serial inter-
face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE goes high, the 22 bits clocked into the
input register on each rising edge of CLK transfers to the
appropriate latch. See Figure 2 for the timing diagram and
Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 ms. This is more than adequate
for systems that have typical lock times in hundreds of
microseconds.
ADuC812 INTERFACE
Figure 34 shows the interface between the ADF420x family and
the
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF420x family
needs a 22-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
On first applying power to the ADF420x family, it requires four
writes (one each to the R counter latch and the AB counter latch
for both RF1 and RF2 sides) for the output to become active.
When operating in the mode described, the maximum
SCLOCK rate of the
maximum rate at which the output frequency can be changed
will be about 180 kHz.
ADuC812
ADuC812
I/O PORTS
Figure 34.
microconverter. Because the
SCLOCK
MOSI
ADuC812
ADuC812
to ADF420x Family Interface
is 4 MHz. This means that the
LE
MUXOUT
(LOCK DETECT)
CLK
DATA
ADuC812
ADF4206/
ADF4208
is based
Rev. A | Page 22 of 24
ADSP-2181 INTERFACE
Figure 35 shows the interface between the ADF420x family and
the
needs a 22-bit serial word for each latch write. The easiest way
to accomplish this using the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for eight bits and use three memory locations for each
22-bit word. To program each 22-bit latch, store the three 8-bit
bytes, enable the autobuffered mode and then write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
ADSP-21xx
ADSP-21xx
Figure 35.
I/O FLAG
digital signal processor. The ADF420x family
SCLK
TFS
DT
ADSP-21xx
ADSP21-xx
to ADF420x Family Interface
LE
CLK
DATA
MUXOUT
(LOCK DETECT)
family is to use the
ADF4206/
ADF4208