ADF4213BCP Analog Devices Inc, ADF4213BCP Datasheet - Page 5

• Manufacturer Part Number: ADF4213BCP
• Description: IC PLL FREQ SYNTHESIZER 20-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF/IF)r

Specifications of ADF4213BCP

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 3GHz

Pin Number
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MUXOUT
AGND
DGND
DGND
Mnemonic
V
V
CP
DGND
RF
AGND
FL
REF
DGND
MUXOUT
CLK
DATA
LE
R
AGND
IF
DGND
CP
V
V
REF
DD
P
P
DD
CP
SET
V
RF
IN
FL
1
2
V
O
DD
RF
IN
IF
RF
RF
RF
P
1
2
IN
IN
O
IF
IN
1
1
10
1
2
3
4
5
6
7
8
9
RF
IF
RF
IF
IF
(Not to Scale)
ADF4210/
ADF4211/
ADF4212/
ADF4213
TOP VIEW
TSSOP
Function
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as
close as possible to this pin. V
the same potential as V
Power Supply for the RF Charge Pump. This should be greater than or equal to V
V
Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
Ground Pin for the RF Digital Circuitry.
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
Ground Pin for the RF Analog Circuitry.
RF/IF Fastlock Mode.
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.
Digital Ground for the IF Digital, Interface and Control Circuitry.
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled
Reference Frequency to be accessed externally.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R
So, with R
Ground Pin for the IF Analog Circuitry.
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry.
Output from the IF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
Power Supply for the IF Charge Pump. This should be greater than or equal to V
V
Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. V
must have the same potential as V
20
19
18
17
16
15
14
13
12
11
DD
DD
DGND
V
V
CP
IF
AGND
R
LE
DATA
CLK
DD
P
1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
SET
IN
2
IF
2
IF
IF
SET
PIN FUNCTION DESCRIPTIONS
= 2.7 kΩ, I
PIN CONFIGURATIONS
DD
I
CP MAX
CP MAX
2.
DD
=
= 5 mA for both the RF and IF Charge Pumps.
1 should have a value of between 2.7 V and 5.5 V. V
ADF4210/ADF4211/ADF4212/ADF4213
DD
R
13 5 .
SET
1.
DD
2 should have a value of between 2.7 V and 5.5 V. V
SET
pin is 0.66 V. The relationship between I
AGND
DGND
CP
RF
FL
RF
RF
RF
IN
O
1
2
3
4
5
20 19
(Not to Scale)
6
ADF4210/
ADF4211/
ADF4212/
ADF4213
TOP VIEW
CP-20
7
18 17
8
DD
9
10
16
/2 and an equivalent input
15
14
13
12
11
DD
DD
DGND
AGND
R
IF
LE
2. In systems where
SET
1. In systems where
IN
IF
IF
DD
1 must have
CP
and R
DD
SET
2
is