CS5526-BSZ Cirrus Logic Inc, CS5526-BSZ Datasheet - Page 15

• Manufacturer Part Number: CS5526-BSZ
• Description: IC ADC 20BIT W/4BIT LATCH 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5526-BSZ

• Number Of Converters: 1
• Package / Case: 20-SSOP
• Number Of Bits: 20
• Data Interface: Serial
• Power Dissipation (max): 12.7mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 3.76 SPs to 616 SPs
• Resolution: 20 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 25 mV
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 25 mV to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1014 - EVAL BOARD FOR CS5526
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1108-5

differential output voltage from the amplifier ex-
ceeds 2.8 V, the amplifier may saturate, which will
cause a measurement error.
The input voltage into the modulator must not
cause the modulator to exceed a low of 20 percent
or a high of 80 percent 1's density. The nominal full
scale input span of the modulator (from 30 percent
to 70 percent 1’s density) is determined by the
VREF voltage divided by the Gain Factor. See Ta-
ble 3 to determine if the CS5525/26 are being used
properly. For example, in the 55 mV range to de-
termine the nominal input voltage to the modulator,
divide VREF (2.5 V) by the Gain Factor (2.2727).
When a smaller voltage reference is used, the re-
sulting code widths are smaller causing the con-
verter output codes to exhibit more changing codes
for a fixed amount of noise. Table 3 is based upon
a VREF = 2.5 V. For other values of VREF, the val-
ues in Table 3 must be scaled accordingly.
Figure’s 8 and 9 illustrate the input models for the
AIN and VREF pins. The dynamic input current for
each of the pins can be determined from the models
shown and is dependent upon the setting of the CFS
(Chop Frequency Select) bit. The effective input
impedance for the AIN+ and AIN- pins remains
constant for the three low level measurement rang-
es (25 mV, 55 mV, and 100 mV). The input current
is lowest with the CFS bit cleared to logic 0.
DS202F5
Note:
Input Range
± 100 mV
± 25 mV
± 55 mV
± 1.0 V
± 2.5 V
± 5.0 V
Table 3. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations
1. The converter's actual input range, the delta-sigma's nominal full scale input, and the delta-sigma's
maximum full scale input all scale directly with the value of the voltage reference. The values in the
table assume a 2.5 V VREF voltage.
(1)
Max. Differential Output
20X Amplifier
2.8 V
2.8 V
2.8 V
-
-
-
(2)
(2)
(2)
VREF
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
Note: Residual noise appears in the converter’s baseband for
output word rates greater than 60 Sps if CFS is logic 0. By set-
ting CFS to logic 1, the amplifier’s chop frequency chops at
32768 Hz eliminating the residual noise, but increasing the
current. Note that C=48pF is for input current modeling only.
For physical input capacitance see ‘Input Capacitance’ spec-
ification under ‘Analog Characteristics’ on page 3.
Figure 9. Input model for VREF+ and VREF- pins.
Gain Factor
2.272727...
Figure 8. Input models for AIN+ and AIN- pins
V
i = fV
n
os
1.25
2.5
1.0
0.5
5
≤ 25 m V
A IN +
A IN
A IN -
os
V R E F +
i = [(V
V R E F -
25m V , 55m V , and 100m V R anges
n
C
i = [(V R E F + ) - (V R E F -)] fC
n
1V , 2 .5 V , and 5V R a nges
C F S = 0 , f = 256 H z
C F S = 1 , f = 32.76 8 kH z
f = 32.768 kH z
A IN +
Differential Input
∆-Σ Nominal
) - (V
f = 3 2 .7 6 8 k H z
± 0.5 V
± 1.1 V
± 2.0 V
± 1.0 V
± 2.5 V
± 5.0 V
A IN -
CS5525 CS5526
C = 32pF
)] fC
(1)
C = 1 6 p F
C = 48pF
Max. Input
± 1.65 V
0V, VA+
± 0.75 V
± 3.0 V
± 1.5 V
± 5.0 V
∆-Σ
(1)
15