ADCS7477AIMF/NOPB National Semiconductor, ADCS7477AIMF/NOPB Datasheet - Page 17

• Manufacturer Part Number: ADCS7477AIMF/NOPB
• Description: IC ADC 10BIT 1MSPS SOT-23-6
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADCS7477AIMF/NOPB

• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADCS7477AIMF; ADCS7477AIMFTR

Applications Information
1.0 ADCS7476/77/78 OPERATION
The ADCS7476/77/78 are successive-approximation analog-
to-digital converters designed around a charge-redistribution
digital-to-analog converter. Simplified schematics of the
ADCS7476/77/78 in both track and hold operation are shown
in
is in track mode: switch SW1 connects the sampling capacitor
to the input, and SW2 balances the comparator inputs. The
device is in this state until CS is brought low, at which point
the device moves to hold mode.
2.0 USING THE ADCS7476/77/78
Serial interface timing diagrams for the ADCS7476/77/78 are
shown in
initiates conversions and frames the serial data transfers.
SCLK (serial clock) controls both the conversion process and
the timing of serial data. SDATA is the serial data out pin,
where a conversion result is found.
Basic operation of the ADCS7476/77/78 begins with CS going
low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled
with reference to the falling edge of CS; for example, "the third
falling edge of SCLK" shall refer to the third falling edge of
SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE,
and the converter moves from track mode to hold mode. The
input signal is sampled and held for conversion at the falling
edge of CS. The converter moves from hold mode to track
mode on the 13th rising edge of SCLK (see
Figure
Figure 4
2, or
Figure
and
Figure
Figure
1, , and
3). The SDATA pin will be placed back into
5, respectively. In
Figure
3. CS is chip select, which
Figure 4
FIGURE 4. ADCS7476/77/78 in Track Mode
FIGURE 5. ADCS7476/77/78 in Hold Mode
the device
Figure
1,
17
Figure 5
nects the sampling capacitor to ground, maintaining the sam-
pled voltage, and switch SW2 unbalances the comparator.
The control logic then instructs the charge-redistribution DAC
to add or subtract fixed amounts of charge from the sampling
capacitor until the comparator is balanced. When the com-
parator is balanced, the digital word supplied to the DAC is
the digital representation of the analog input voltage. The de-
vice moves from hold mode to track mode on the 13th rising
edge of SCLK.
TRI-STATE after the 16th falling edge of SCLK, or at the rising
edge of CS, whichever occurs first. After a conversion is com-
pleted, the quiet time t
CS low again to begin another conversion.
Sixteen SCLK cycles are required to read a complete sample
from the ADCS7476/77/78. The sample bits (including any
leading or trailing zeroes) are clocked out on falling edges of
SCLK, and are intended to be clocked in by a receiver on
subsequent falling edges of SCLK. The ADCS7476/77/78 will
produce four leading zeroes on SDATA, followed by twelve,
ten, or eight data bits, most significant first. After the data bits,
the ADCS7477 will clock out two trailing zeros, and the
ADCS7478 will clock out four trailing zeros. The ADCS7476
will not clock out any trailing zeros; the least significant data
bit will be valid on the 16th falling edge of SCLK.
Depending upon the application, the first edge on SCLK after
CS goes low may be either a falling edge or a rising edge. If
the first SCLK edge after CS goes low is a rising edge, all four
leading zeroes will be valid on the first four falling edges of
shows the device in hold mode: switch SW1 con-
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must be satisfied before bringing
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