MAX11612EUA+ Maxim Integrated Products, MAX11612EUA+ Datasheet - Page 5

• Manufacturer Part Number: MAX11612EUA+
• Description: IC ADC SERIAL 12BIT 4CH 8-MSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX11612EUA+

• Number Of Bits: 12
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 362mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution: 12 bit
• Interface Type: I2C
• Snr: 70 dB
• Voltage Reference: 4.096 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Power Dissipation: 470.6 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 5 V
• Minimum Operating Temperature: - 40 C
• For Use With: MAXSPCSPARTAN6+ - ADC and DAC Eval Expansion Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS (Figure 1) (continued)
(V
(MAX11613/MAX11615/MAX11617), V
otherwise noted. Typical values are at T
Note 1: All WLP devices are 100% production tested at T
Note 2: For DC accuracy, the MAX11612/MAX11614/MAX11616 are tested at V
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
Note 10: Measured as for the MAX11613/MAX11615/MAX11617:
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
Serial-Clock Frequency
Hold Time, Repeated START
Condition (Sr)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
DD
= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V
design and characterization.
MAX11613/MAX11615/MAX11617are tested at V
offsets have been calibrated.
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit ).
PARAMETER
⎡
⎢
⎢
⎣
[
V
FS
( .
3 6
_______________________________________________________________________________________
V
( .
)
3 6
−
V
FS
V
−
( .
2 7
12-Bit ADCs in Ultra-Small Packages
2 7
.
V
V
)
)
]
SYMBOL
t
t
t
t
t
REF
HD
HD, STA
SU
SU
SU
×
f
t
t
t
A
t
SCLH
HIGH
t
RCL1
t
t
LOW
RDA
RCL
FDA
t
FCL
C
,
,
SP
,
,
Low-Power, 4-/8-/12-Channel, I
2
= +25°C, see Tables 1–5 for programming notation.) (Note 1)
V
B
STA
DAT
DAT
STO
= 4.096V (MAX11612/MAX11614/MAX11616), f
N
REF
−
1
⎤
⎥
⎥
⎦
(Note 14)
(Note 11)
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
(Notes 11 and 14)
DD
A
= +25°C. Specifications over temperature limits are guaranteed by
B
DD
= 3V. All devices are configured for unipolar, single-ended inputs.
= 400pF, Note 13)
= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V
CONDITIONS
DD
DD
DD
DD
- 0.7V
- 0.7V
- 0.7V
- 0.7V
DD
DD
DD
DD
DD
(Note 12)
P-P
= 5V and the
.
SCL
= 1.7MHz, T
DD
MIN
.
160
320
120
160
160
10
20
20
20
20
20
0
0
A
TYP
= T
MIN
MAX
to T
150
160
160
160
400
1.7
80
80
10
REF
MAX
= 2.048V
2
, unless
UNITS
MHz
pF
C,
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5