AD9233BCPZ-125 Analog Devices Inc, AD9233BCPZ-125 Datasheet - Page 20

• Manufacturer Part Number: AD9233BCPZ-125
• Description: IC ADC 12BIT 80/105/125 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9233BCPZ-125

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Number Of Converters: 3
• Power Dissipation (max): 425mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 12bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9233-125EBZ - BOARD EVALUATION FOR AD9233
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9233
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9233. Power
supplies for clock drivers should be separated from the ADC
output driver supplies to avoid modulating the clock signal with
digital noise. The power supplies should also not be shared with
analog input circuits such as buffers to avoid the clock
modulating onto the input signal or vice versa. Low jitter,
crystal-controlled oscillators make the best clock sources.
If the clock is generated from another type of source (by
gating, dividing, or other methods), it should be retimed by the
original clock at the last step.
Refer to Application Notes AN-501, Aperture Uncertainty and
ADC System Performance, and AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter for more in-depth
information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 52 and Figure 53, the power dissipated by
the AD9233 is proportional to its sample rate. The digital power
dissipation is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current (I
where N is the number of output bits (12 in the case of the
AD9233).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption.
The data used for Figure 52 and Figure 53 is based on the
same operating conditions as used in the plots in the Typical
Performance Characteristics section with a 5 pF load on each
output driver.
I
DRVDD
DRVDD
=
V
) can be calculated as
DRVDD
CLK
×
/2. In practice, the DRVDD current is
C
LOAD
×
f
CLK
2
×
N
Rev. A | Page 20 of 44
Figure 52. AD9233-125 Power and Current vs. Clock Frequency, F
Figure 53. AD9233-105 Power and Current vs. Clock Frequency, F
Figure 54. AD9233-80 Power and Current vs. Clock Frequency, F
290
275
260
245
230
215
410
390
370
350
330
310
290
270
250
475
450
425
400
375
350
325
0
5
0
IAVDD
IAVDD
IAVDD
TOTAL POWER
25
20
30
CLOCK FREQUENCY (MSPS)
TOTAL POWER
CLOCK FREQUENCY (MSPS)
CLOCK FREQUENCY (MSPS)
TOTAL POWER
50
40
55
IDRVDD
IDRVDD
IDRVDD
75
60
80
100
IN
80
IN
IN
105
125
= 30 MHz
150
120
90
60
30
0
= 30 MHz
= 30 MHz
200
180
160
140
120
100
80
60
40
20
0
250
200
150
100
50
0