MAX1383ATP+ Maxim Integrated Products, MAX1383ATP+ Datasheet - Page 18

• Manufacturer Part Number: MAX1383ATP+
• Description: IC ADC 12BIT 1.25MSPS 20-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1383ATP+

• Number Of Bits: 12
• Sampling Rate (per Second): 1.25M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 85.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-WQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
DOUT1 (and DOUT2, if S/D = low) transitions from high
impedance to being actively driven low once the ADC
enters hold mode. DOUT_ remains low for the first three
SCLK pulses and begins outputting the conversion result
after the 4th rising edge of SCLK, MSB first. DOUT_ tran-
sitions complete t
the DOUT_ values remain valid for t
rising edge of SCLK. A total of 16 SCLK pulses are
required to complete a normal conversion in dual-output
mode and 28 SCLK pulses in single-output mode.
DOUT_ goes low after the 16th rising edge of SCLK and
goes high-impedance when CNVST goes high.
Figure 8. Dual-Output CNVST Transition Modes
Figure 9. Dual-Output Mode, Single and Continuous Conversions
18
______________________________________________________________________________________
CNVST
CNVST
DOUT_
DOUT_
SCLK
SCLK
SCLK
SINGLE CONVERSION
CONTINUOUS CONVERSION
CNVST
*CNVST MUST GO HIGH BETWEEN THE 14TH RISING AND 16TH FALLING EDGES OF SCLK.
TO MAINTAIN CONTINUOUS CONVERSIONS, DOUT_ REMAINS LOW BETWEEN
CONVERSION RESULTS IN CONTINUOUS-CONVERSION DUAL-OUTPUT MODE.
CS
HIGH-Z
DOUT
1
1
0
0
after each SCLK rising edge and
0
0
1
0
0
2
D11
D11
HOLD
D10
3
D10
after the next
D9
D9
4
POWER-DOWN
D8
D8
8
8
D7
CONTINUOUS MODE
14
D7
For continuous operation in single-output mode, pull
CNVST high after the 14th rising and before the 28th
rising edge of SCLK. In dual-output mode, if CNVST
returns high after the 14th rising and before the 16th
falling edge of SCLK, DOUT_ remains active so continu-
ous conversions can be sustained. If CNVST is low
during the 16th edge of SCLK (dual-conversion mode)
and the 28th falling edge of SCLK (single-output mode),
DOUT_ returns to its high-impedance state on the next
rising edge of CNVST or SCLK, enabling the serial inter-
face to be shared by multiple devices. See Figures 9
and 10 for single and continuous conversion timing
diagrams.
9
9
15
D6
D6
D5
16
DOUT_ HI-Z
D5
D4
D4
DOUT_ HI-Z
17
D3
D3
D2
CONTINUOUS-CONVERSION
SELECTION WINDOW*
D2
14
D1
D1
D0
D0
16
16
HIGH-Z
1