LTC1283ACN#PBF Linear Technology, LTC1283ACN#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC1283ACN#PBF
• Description: IC DATA ACQ SYS 10BIT 3V 20-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS)r

Specifications of LTC1283ACN#PBF

• Resolution (bits): 10 b
• Sampling Rate (per Second): 15k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Dual ±
• Voltage - Supply: 3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSB-First/LSB-First Format (MSBF)
The output data of the LTC1283 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. For MSB-
first output data the input word clocked to the LTC1283
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data, the input
word clocked to the LTC1283 should always contain a zero
in the MSBF bit location. The MSBF bit in a given D
will control the order of the next D
affects only the order of the output data word. The order
of the input word is unaffected by this bit.
Word Length (WL1, WL0)
The last two bits of the input word (WL1 and WL0)
program the output data word length of the LTC1283.
Word lengths of 8-, 10-, 12- or 16-bit can be selected
according to the following table. The WL1 and WL0 bits in
a given D
next, D
and must be set for the correct D
when a “dummy” D
the word length should be made equal to the number of
SCLK cycles sent by the MPU.
Figure 2 shows how the data output (D
controlled with word length selection and MSB/LSB-first
format selection.
3. Deglitcher
A deglitching circuit has been added to the chip select
input of the LTC1283 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
A
PPLICATI
WL1
0
0
1
1
OUT
MSBF
IN
0
1
word. WL1 and WL2 are never “don’t cares”
word control the length of the present, not the
WL0
O
0
1
0
1
IN
U
word is sent. On any transfer cycle,
S
I FOR ATIO
U
OUTPUT WORD LENGTH
OUTPUT FORMAT
OUT
OUT
MSB-First
LSB-First
W
word. The MSBF bit
10 Bits
12 Bits
16 Bits
8 Bits
OUT
word length even
) timing can be
U
IN
LTC1283 • AI09
word
LTC1283 AI08
1 ACLK cycle. After a change of state on the CS input, the
LTC1283 waits for two falling edges of the ACLK before
recognizing a valid chip select. One indication of CS low
recognition is the D
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
4. CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time (see Figure 3). The serial port
ignores any SCLK activity while CS is high. The LTC1283
will also operate with CS low during the conversion. In this
mode, SCLK must remain low during the conversion as
shown in Figure 4. After the conversion is complete, the
D
the data transfer can begin as normal.
5. Microprocessor Interfaces
The LTC1283 can interface directly (without external hard-
ware) to most popular microprocessor (MPU) synchro-
nous serial formats (see Table 2). If an MPU without a
serial interface is used, then four of the MPU’s parallel port
lines can be programmed to form the serial link to the
LTC1283. Included here are three serial interface ex-
amples and one example showing a parallel port pro-
grammed to form the serial interface.
OUT
ACLK
ACLK
D
D
OUT
OUT
CS
CS
line will become active with the first output bit. Then
VALID OUTPUT
HI-Z
HIGH CS RECOGNIZED INTERNALLY
LOW CS RECOGINZED INTERNALLY
OUT
line becoming active (leaving the
VALID OUTPUT
LTC1283
HI-Z
11
LTC1283 • AI10
1283fb