ISP1181BBS,557 NXP Semiconductors, ISP1181BBS,557 Datasheet - Page 36

• Manufacturer Part Number: ISP1181BBS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1181BBS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Table 33.
ISP1181B_3
Product data sheet
Bit
Symbol
Reset
Access
Endpoint Status Image Register: bit allocation
12.2.5 Clear Endpoint Buffer
12.2.6 Check Endpoint Status
EPSTAL
R
7
0
This command unlocks and clears the buffer of the selected OUT endpoint, allowing the
reception of new packets. Reception of a complete packet causes the Buffer Full flag of an
OUT endpoint to be set. Any subsequent packets are refused by returning a NAK
condition, until the buffer is unlocked using this command. For a double-buffered endpoint
this command switches the current FIFO for CPU access.
Remark: For special aspects of the control OUT endpoint see
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none
This command is used to check the status of the selected endpoint FIFO without clearing
any status or interrupt bits. The command accesses the Endpoint Status Image Register,
which contains a copy of the Endpoint Status Register. The bit allocation of the Endpoint
Status Image Register is shown in
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
Table 34.
Bit
7
6
5
4
3
2
1
0
EPFULL1
R
6
0
Endpoint Status Image Register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
EPFULL0
R
5
0
Rev. 03 — 23 January 2009
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled,
0 = not stalled).
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA0 PID,
1 = DATA1 PID).
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it was
acknowledged or before the endpoint was stalled. This bit is cleared
by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1 the
firmware must stop ongoing setup actions and wait for a new Setup
packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU access
(0 = primary buffer, 1 = secondary buffer).
reserved
DATA_PID
R
4
0
Table
33.
WRITE
OVER
R
3
0
Full-speed USB peripheral controller
SETUPT
R
2
0
Section
CPUBUF
© ST-NXP Wireless 2009. All rights reserved.
ISP1181B
R
1
0
9.5.
reserved
R
0
0
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