ISP1181BBS,557 NXP Semiconductors, ISP1181BBS,557 Datasheet - Page 42

• Manufacturer Part Number: ISP1181BBS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1181BBS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

ISP1181B_3
Product data sheet
Fig 8.
Interrupt logic.
interrupt register
interrupt enable
RESUME
IEP0OUT
SUSPND
EP0OUT
IERESM
IESUSP
RESET
register
IEP0IN
EP0IN
IERST
IESOF
IEEOT
IEP14
EP14
The active level and signalling mode of the INT output is controlled by the INTPOL and
INTLVL bits of the Hardware Configuration Register (see
reset are active LOW and level mode. When pulse mode is selected, a pulse of 166 ns is
generated when the OR-ed combination of all interrupt bits changes from logic 0 to
logic 1.
Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the Interrupt
Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated
Endpoint Status Register.
Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the current
bus status when reading the Interrupt Register.
SETUP and OUT token interrupts are generated after ISP1181B has acknowledged the
associated data packet. In bulk transfer mode, the ISP1181B will issue interrupts for every
ACK received for an OUT token or transmitted for an IN token.
In isochronous mode, an interrupt is issued upon each packet transaction. The firmware
must take care of timing synchronization with the host. This can be done via the Pseudo
Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt Enable Register.
If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows the
firmware to keep data transfer synchronized with the host. After 3 missed SOF events the
ISP1181B will enter ‘suspend’ state.
An alternative way of handling isochronous data transfer is to enable both the SOF and
the PSOF interrupts and disable the interrupt for each isochronous endpoint.
SOF
EOT
...
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Rev. 03 — 23 January 2009
hardware configuration
device mode
INTENA
INTPOL
INTLVL
register
register
Full-speed USB peripheral controller
GENERATOR
Table
PULSE
1
0
21). Default settings after
MGS772
© ST-NXP Wireless 2009. All rights reserved.
INT
ISP1181B
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