GD16334100BA Intel, GD16334100BA Datasheet - Page 2

• Manufacturer Part Number: GD16334100BA
• Manufacturer: Intel

Specifications of GD16334100BA

• Operating Temperature (max): 85C
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Functional Details
Synchronisation
The GD16334 provides a synchronisa-
tion block that allows parallel operation of
multiple devices for wider data width.
When this is required only the synchroni-
sation block in one GD16334 device is
used as master controller, which drives
the synchronisation input of all parallel
connected (slave) MUX devices.
The synchronisation block provides a
clock output (FCKO) and a SYNCO sig-
nal (which is a 1/8 clock signal) timed by
the FCKO output. These signals are then
daisy-chained to the CLK and SYNC in-
puts of all the MUX devices. This solution
provides a fully synchronised parallel
multiplexer structure, where all MUX data
ports samples data in the same clock
cycle.
Figure 1. GD16255: 10 Gbit/s, STM64
Data Sheet Rev. 10
Termination
32
32
32
32
transmitter application.
I0
I31
SYNC
CLK
FCK
I0
I31
SYNC
CLK
FCK
I0
I31
SYNC
CLK
FCK
I0
I31
SYNC
CLK
FCK
GD16334
GD16334
GD16334
GD16334
SYNCO
SYNCO
SYNCO
SYNCO
FCKO
FCKO
FCKO
FCKO
O0
O1
O2
O3
O0
O1
O2
O3
O0
O1
O2
O3
O0
O1
O2
O3
4
4
4
4
or 50
The data inputs (FCK, CLK and SYNC)
allow for either CML or PECL termina-
tion. Termination resistors must be pro-
vided externally (i.e. 50
and SYNCO outputs are both open drain
outputs accommodating the CLK and
SYNC inputs in CML configuration.
There are two ways to connect the mas-
ter clock, provided at the input to the
GD16334’s from the upstream device,
with different timing constrains. Using the
clock output (FCKO) from the synchroni-
sation block, will give a good timing con-
dition for the SYNC signal path, with
respect to the clock. But it will put con-
strains on the timing at the data outputs,
since the synchronisation block will add a
delay to the master clock, with respect to
the data coming from the upstream de-
vice (refer to Figure 1).
16
to V
CKO
-2 V if PECL). The FCKO
GD16334
GD16255
Laser Driver
to V
GD19901
GD19903
LDD
e.g.
if CML
Laser
Another approach is to feed the input
clock directly to the CLK input of the
MUX’es, maintaining the data/clock rela-
tions as given by the upstream device.
This will however put constrains on the
timing of the SYNC signal path. De-
pending on actual timing of the upstream
device and actual board layout, both ap-
proaches may prove applicable.
In either case, to compensate for board
delays use the far-end device as clock
master such that the clock propagating
the slave devices compensates delay on
data propagating to the GD16255.
Counter Clocking
Counter Clocking
Figure 2. Maintaining fast clock < - >
Practical Considerations
The SYNC and CLK control signals are
differential high-speed control signals.
Care should be taken to design the rout-
ing of these signals as transmission
lines, i.e. as coplanar wave guides, or as
strip lines. The signals should be routed
without branches from the signal source
with shortest possible distance to the first
load, then onwards to the next load, and
finally terminating in a resistor matching
the transmission line impedance, nor-
mally 50 . The transmission line should
not have any branches in order to mini-
mise stub effects (reflections).
78 MHz Clock
78 MHz Clock
32
32
data relations
I0
I31
SYNC
CLK
I0
I31
SYNC
CLK
GD16334
GD16334
SYNCO
SYNCO
CKO
CKO
O0
O1
O2
O3
O0
O1
O2
O3
Page 2
Counter Clocking
4
4
622 MHz Clock