MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet - Page 33

• Manufacturer Part Number: MT48H4M16LFB4-75
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-75

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 28:
WRITE with Auto Precharge
PDF: 09005aef8237ed98, Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN
READ with Auto Precharge Interrupted by a WRITE
Note:
3. Interrupted by a READ (with or without auto precharge): When a READ to bank m reg-
4. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
Internal
States
isters, it will interrupt a WRITE on bank n, with the data-out appearing 2 or 3 clocks
later, (depending on CAS latency). The precharge to bank n will begin after
met, where
to bank n will be data-in registered one clock prior to the READ to bank m (Figure 29
on page 34).
registers, it will interrupt a WRITE on bank n. The precharge to bank n will begin after
t
data WRITE to bank n will be data registered one clock prior to a WRITE to bank m
(see Figure 30 on page 34).
WR is met, where
DQM is HIGH at T2 to prevent D
COMMAND
ADDRESS
BANK m
BANK n
DQM
CLK
DQ
t
WR begins when the READ to bank m is registered. The last valid WRITE
1
Active
Page
READ - AP
BANK n,
BANK n
COL a
T0
READ with Burst of 4
t
WR begins when the WRITE to bank m is registered. The last valid
CAS Latency = 3 (BANK n)
Page Active
T1
NOP
33
T2
NOP
OUT
a + 1 from contending with D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
D
NOP
OUT
a
64Mb: 4 Meg x 16 Mobile SDRAM
BANK m,
WRITE - AP
COL d
BANK m
T4
D
d
IN
Interrupt Burst, Precharge
WRITE with Burst of 4
T5
d + 1
NOP
D
IN
t
RP - BANK n
T6
d + 2
NOP
D
DON’T CARE
IN
©2006 Micron Technology, Inc. All rights reserved.
IN
T7
t WR - BANK m
d + 3
NOP
D
d at T4.
IN
Write-Back
Idle
t
WR is