PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet
PEF82902FV11XP
Specifications of PEF82902FV11XP
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PEF82902FV11XP Summary of contents
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Edition 2001-11-09 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms ...
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PEF 82902 Revision History: Previous Version: Page Subjects (major changes since last revision) Table 18 Additional C/I-command LTD Figure 41 Chapter 2.4.7.4 Chapter 3.2.3 The Framer / Deframer Loopback (DLB more supported Chapter 4.3 Chapter 4.9.4 Chapter 4.3 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.4.4.2 Block Error Counter (RDS Error Counter 2.4.5 Scrambler / Descrambler . . . . ...
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Table of Contents 4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.7.12 ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . 150 4.7.13 MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . ...
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Table of Contents 7.3 External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 42 State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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Overview The PEB 82902 (T-SMINT interface. A microcontroller interface provides access to both transceivers as well as the â IOM -2 interface. However, as opposed to its bigger brother T-SMINT an HDLC controller. Main target applications of the T-SMINT ...
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References [1] TS 102 080, Transmission and Multiplexing; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 [2] FTZ 1 TR 220 Technische Richtlinie, Spezifikation der ISDN Schnittstelle Uk0 Schicht 1, Deutsche Telecom AG, ...
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T-SMINT I 4B3T Second Gen. Modular ISDN NT (Intelligent) Version 1.1 1.2 Features • Features known from the PEB 8090 • U-transceiver and S-transceiver on one chip • U-interface (4B3T) conform to ETSI [1] and FTZ [2]: – Meets ...
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Enhanced IOM interface – Timeslot access and manipulation (SCOUT) – BCL output; programmable and flexible strobes SDS1/2, e.g. active during several timeslots. – Optional: All registers can be read and written to via new Monitor channel concept – ...
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Pin Configuration • /VDDDET 49 50 VDDa_SR 51 52 VSSa_SR XOUT 59 XIN 60 BOUT ...
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Block Diagram • SR1 SR2 SX1 S-Transceiver SX2 TP1 Factory Tests TP2 IOM-2 Interface FSC DCL BCL DU DD Figure 2 Block Diagram Data Sheet XIN XOUT VDDDET Clock Generation POR/UVD D-Channel Arbitration (e.g. Multiplexed Mode) ...
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Pin Definitions and Functions • Table 2 Pin Definitions and Functions Pin Symbol VDDa_UR 2 VSSa_UR 1 VDDa_UX 62 VSSa_UX 63 VDDa_SR 51 VSSa_SR 52 VDDa_SX 46 VSSa_SX 45 VDDD 29 VSSD 30 VDDD 13 VSSD 14 FSC 32 ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol SDS1 8 SDS2 SCLK 26 AD5 26 SDR 27 AD6 27 Data Sheet Type Function O Serial Data Strobe1: Programmable strobe signal for time slot and/or D-channel indication ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol SDX 28 AD7 28 AD0 21 AD1 22 AD2 23 AD3 24 AD4 ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 10 WR R/W ALE 9 RST 5 RSTO 6 INT 15 MCLK 18 EAW 20 SX1 43 SX2 44 SR1 47 Data Sheet Type Function I Write Indicates a write access ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol SR2 48 XIN 60 XOUT 59 AOUT 64 BOUT 61 AIN 3 BIN 4 VDDDET 49 ACT 17 TP1 42 TP2 50 16, 19, 41, 55 res 56, 57 ...
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I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.6.1 Specific Pins and Test Modes LED Pin ACT A LED can be connected to pin ACT to display four different states (off, slow flashing, fast flashing, on). It displays the ...
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System Integration • S/T - Interface POTS Interface HV - SLIC SLICOFI - SLIC USB / V.24 Interface Figure 3 Application Example T-SMINT The U-transceiver, the S-transceiver and the IOM monitored via: a) the parallel or ...
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IOM-2 Slave e.g. SLICOFI-2 Figure 4 Control via µP Interface Alternatively, the T-SMINT â b) the IOM -2 Interface - Access of on-chip registers via the Monitor channel with Header/Address/Data format (Device is Monitor slave) - Activation/Deactivation control of ...
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S IOM -2 IOM-2 Master e.g. UTAH Figure 5 Control via IOM Data Sheet C/I1 C/I0 MON INT â -2 Interface 15 PEF 82902 Overview U Register iomslave.vsd 2001-11-09 ...
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Functional Description 2.1 Microcontroller Interfaces â The T-SMINT I supports either a serial or a parallel microcontroller interface. For applications where no controller is connected to the T-SMINT interface, register programming is done via the IOM master device. In ...
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The T-SMINT edge of SCLK and shifts out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. Data is transferred in groups of 8 bits ...
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Write Access CS SCLK SDR SDX Read Access CS SCLK SDR SDX Figure 6 Serial Control Interface Timing Data Sheet Header Command/Address ...
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Programming Sequences The basic structure of a read/write access to the T-SMINT control interface is shown in • write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 7 Serial Command Structure A new programming sequence starts ...
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Example for a read/write access with header 40 SDR header wradr SDX Header 48 : Interleaved A-D-A-D Sequences H The interleaved A-D-A-D sequences give direct read/write access to the address range 00 -7F ...
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Example for a read/write access with header 41 SDR header rdadr SDX Header 49 : Interleaved A-D-D-D Sequence H This sequence (header 49 A-D-A-D read access. Generally, it can be used for any register access to the address range 20 ...
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In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE before a read/write access via the address/data bus is performed. â The T-SMINT I provides two different ways to address the register contents which can ...
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Microcontroller Clock Generation The microcontroller clock is derived from the unregulated 15.36 MHz clock from the oscillator and provided by the pin MCLK. Five clock rates are selectable by a programmable prescaler which is controlled by the bits MODE1.MCLK ...
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C/I0 Code Change (Exchange Awake 125µs Watchdog Software Reset Register (SRES) RES_CI Reset RES_HDLC Functional Block RES_S RES_U Internal Reset of all Registers Figure 9 Reset Generation of the T-SMINT Reset Source Selection The internal reset ...
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The internal reset sources set the MODE1 register to its reset value. Table 8 Reset Source Selection RSS2 RSS1 Bit 1 Bit POR/UVD can be enabled/disabled via pin VDDDET • ...
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External Reset Input At the RST input an external reset can be applied forcing the T-SMINT state. This external reset signal is additionally fed to the RSTO output. After release of an external reset, the C has to wait for ...
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IOM -2 Interface â The T-SMINT I supports the IOM â according to the IOM -2 Reference Guide [12]. â 2.3.1 IOM -2 Functional Description â The IOM -2 interface consists of four lines: FSC, DCL, DD, DU and ...
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The frame is composed of three channels: • Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of e.g. the U-transceiver. • Channel ...
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Figure 11 Architecture of the IOM Data Sheet Functional Description CDA Data Monitor Data TIC Bus Data C/I0 Data C/I1 Data D/B1/B2 Data C/I0 Data â -2 Handler 29 PEF 82902 DU DD FSC DCL BCL/SCLK SDS1 SDS2 2001-11-09 ...
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Controller Data Access (CDA) The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access to the 12 IOM • looping four independent PCM channels from vice versa over the ...
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TSa 1 0 Enable output (EN_O0) CDAx0 1 0 TSa a,b = 0...11 Figure 12 Data Access via CDAx0 and CDAx1 register pairs Looping and Shifting Data Figure 13 gives examples for typical configurations ...
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Looping Data .TSS: .DPS .SWAP b) Shifting Data TSa CDA10 TSa .TSS: .DPS .SWAP c) Switching Data TSa CDA10 TSa .TSS: .DPS .SWAP Figure 13 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) ...
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Figure 14 shows the timing of looping TSa from via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data ...
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Shifting TSa TSb within one frame (a,b: 0...11 and b a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa (DD) CDAxy ...
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Monitoring Data Figure 16 gives an example for monitoring of two IOM simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the channel registers ...
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DD. By this it is possible to monitor the TIC bus (TS11) and h the odd numbered D-channel (TS3) simultaneously on DU and DD. Synchronous Transfer While looping, shifting and switching the data can be ...
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Table 9 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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INT CIC CIC 1 0 WOV WOV S S MOS MOS 1 0 MASK ISTA Figure 17 Interrupt Structure of the Synchronous Data Transfer Figure 18 shows some examples based on the timeslot structure. Figure ...
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STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 b) Interrupts for data ...
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Serial Data Strobe Signal For time slot oriented standard devices at the IOM two independent data strobe signals SDS1 and SDS2. The two strobe signals can be generated with every 8-kHz-frame and are controlled by the registers SDS1/2_CR. By ...
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Figure 19 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM and MON1. The third example shows a strobe signal for 2B+D channels which is used e.g. ...
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The MONITOR channel protocol is described In the following section and shall illustrate this. The relevant control and status bits for transmission and reception are listed in Table 10 and Table 10 Transmit Direction Control/ Register Status Bit Control MOCR ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 20 MONITOR Channel Protocol (IOM Before ...
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MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to ’1’ result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA ...
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Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two ...
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IOM -2 Frame No. MX (DU) MR (DD) Figure 21 Monitor Channel, Transmission Abort requested by the Receiver • IOM -2 Frame No. MR (DU) MX (DD) Figure 22 Monitor Channel, Transmission Abort requested by the Transmitter • IOM ...
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MONITOR Channel Programming as a Master Device The master mode is selected by default if one of the microcontroller interfaces is selected. The monitor data is written by the microcontroller in the MOX register and â transmitted via IOM ...
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DU 1st byte value DU 2nd byte value DU 3rd byte value DU 4th byte value DU (nth + 3) byte value All registers can be read back when setting the R/W bit to ’1’. The T-SMINT â by ...
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MASK U ST CIC 1 WOV S MOS 1 INT Figure 24 MONITOR Interrupt Structure 2.3.4 C/I Channel Handling The Command/Indication channel carries real-time status information between the T- â SMINT I and another device connected to the IOM ...
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In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). The ...
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D-Channel Access Control The upstream D-channel is arbitrated between the S-bus and external HDLC controllers via the TIC bus (S/G, BAC, TBA bits) according to the IOM Further to the implementation in the INTC possible, to set ...
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T-SMINT E-Bit S D Figure 27 D-Channel Arbitration: C with HDLC and no Access to TIC Bus 2.3.5.2 TIC Bus Handling The TIC bus is implemented to organize the access to the C/I0-channel and to the D- channel from ...
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Figure 28 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the T-SMINT occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is withdrawn. After a ...
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MON Figure 29 Structure of Last Octet of Ch2 on DD 2.3.5.4 D-Channel Arbitration In intelligent NT applications (selected via register S_MODE.MODE2-0) the T-SMINT has to share the upstream D-channel with one or more D-channel ...
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Table 12 T-SMINT I Configuration Settings in Intelligent NT Applications Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit and TIC bus evaluation Note: For mode selection in the S_MODE register the ...
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D=0) & [BAC = 1 or (BAC = 0 & CNT BAC = d.c. DCI = 0 S ACCESS S Setting DCI = 1 causes ...
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T-SMINT I S-transceiver transmits inverted echo channel (E bits) on the S-bus to block all connected S-bus terminals (E = D). • Local D-channel source commences with D data transmission on IOM it receives S/G = “0”. • After ...
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FSC DI DIN DR DOUT b) DCL DIN D Figure 31 Deactivation of the IOM Conditions for Power-Down If none of the following conditions is true, the IOM reducing power consumption to a minimum. • S-transceiver is not ...
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Activation from the U-interface 2.4 U-Transceiver The statemachine of the U-Transceiver is compatible to the NT state machine in the PEB 8090 documentation [9], but includes some minor changes for simplification and compliance to Ref. [1]. The U-transceiver is ...
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Performance requirements according to ETSI TS 102 080 are met, too frames are transmitted via the U-interface, each consisting of: • 108 symbols: 144 bit scrambled and coded data • 11 symbols: Barker ...
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Table 13 Frame Structure A for Downstream Transmission 1/2 1/2 1 ...
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Table 14 Frame Structure B for Upstream Transmission 1/2 1/2 1 ...
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Maintenance Channel The 4B3T frame structure provides a 1 kbit/s M(aintenance)-channel for the transfer of remote loopback commands and error indications. Loopback Commands The LT station uses the M-channel to request remote loopbacks. Loopback commands are coded with a ...
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Table 15 MMS 43 Coding Table – ...
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Table 16 4B3T Decoding Table – 0 – – – 2.4.4.1 Monitoring of Code Violations The running digital sum monitor (RDSM) computes the running digital sum from the received ternary ...
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Note that every frame with a detected code violation causes about binary bit errors on average bit error rate of 10 frame errors within 1000 s in the LT (1 frame error detected in the ...
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C/I code ‘1010‘ must not be input to the U-transceiver. • AI Activation Indication AIL Activation Indication Loop 2 AR Activation Request ARL Activation Request Local ...
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Figure 32 State Diagram Example Each state has one or more transitions to other states. These transitions depend on certain conditions which are noted next to the transition lines. These conditions are the only possibility to leave a state. If ...
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LT INFO U2W 2.133 ms NT Figure 33 Awake Procedure initiated by the LT • INFO U1W 2.133 ms Figure 34 Awake Procedure initiated by the NT Acting as Calling Station After sending the awake signal, the ...
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Acknowledging a Wake-Up Call If a deactivated device detects an awake signal acknowledge signal is sent out. After that, the U-transceiver waits for a possible repetition of the awake signal (in case the acknowledge hasn’t been recognized). ...
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NT State Machine (IEC-T / NTC-T Compatible) • T6S T6E Awake Signal Sent T13E Ack. Sent / Received T12S U1A (U0 & T12E) Synchronizing RSY SBC Synchronizing LOF AR / ARL Wait for ...
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Table 19 Differences to the former NT-SM of the IEC-T/NTC-T No. State/ Signal Change 1. State ’Deact. split into 3 states Request Rec.’ - ’Pend. Deactivation 1’ - ’Reset’ State - ’Test’ State 2. State ’Loss of new inserted, ...
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LTD LT Disable This unconditional command forces the U-transceiver to state ’Test’, where it transmits U0. No further action is initiated. RES Reset Unconditional command which resets the U-transceiver. SSP Send Single Pulses Unconditional command which requests the transmission of ...
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Table 20 Timers (cont’d) Timer Duration (ms) T12 12 T13 13 2.4.7.5 Outputs of the U-Transceiver Below the signals and indications are summarized that are issued on IOM indications) and on the U-interface (predefined U-signals). C/I Indications AI Activation Indication ...
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Signals on U-Interface The signals U0, U1W, U1A, U1, U3, U5 and SP are transmitted on the U-interface.They are defined in Table 25. ® Signals on IOM -2 The Data (B+B+D) is set to all ’1’s in all states besides ...
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Awake Signal Sent The NT has sent out the awake signal U1W and waits now for a response. If the LT does not react in time timer T6 expires and the NT repeats its wake-up call. Deactivated Only in “Deactivated” ...
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Synchronizing After the successful awake procedure the U-transceiver trains its receiver coefficients until it is able to detect the signals U2. Reset In state ’Reset’ a software-reset is performed. Test State “Test” is entered when the unconditional commands C/I=SSP is ...
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UCIR C/I C/I C/I 0 C/I intstruct_4b3t.emf Figure 36 Interrupt Structure U-Transceiver Data Sheet ISTAU MASKU RDS RDS 1ms 1ms 0 ...
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S-Transceiver The S-Transceiver offers the NT and LT-S mode state machines described in the User’s Manual V3.4 [8]. The S-transceiver lies in IOM via the registers described in but can be set to LT-S mode via register programming. The ...
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Figure 38 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N ...
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S/Q Channels, Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q- channel). The Q bits are defined to be ...
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S data will be inserted at the downstream (NT (see Table 24). Access to S2-S5-channel is not supported. Interrupt Handling for Multi-Framing To trigger the microcontroller for a multi-frame access an interrupt can be generated once per multi-frame (SQW) or ...
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C/I Command IOM-2 C/I Indication Figure 39 S-Transceiver Control The state diagram notation is given in The information contained in the state diagrams are: – state name – Signal received from the line interface (INFO) – Signal transmitted to ...
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IOM-2 Interface C/I code S/T Interface INFO Figure 40 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “ ” stands for a logical AND combination. And a ...
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C/I Codes in Reset State In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a hardware reset (RST) or with the C/I code RES. C/I Codes in Deactivated State If the S-transceiver ...
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Receive Infos on S/T I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 Transmit Infos on S/T I0 INFO 0 I2 INFO 2 I4 INFO 4 It ...
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State Machine NT Mode • RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 Lost Framing U i2 ...
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G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM G1 I0 Detected An ...
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G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands • Command Abbr. Deactivation ...
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Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code Ciolation CVR Activation Indication AI Deactivation DI Indication Data Sheet Code Remark 1110 Activation Indication Loop 1111 Deactivation ...
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State Machine LT-S Mode • RST TIM RES DR Reset i0 * RES DC Any State DC RSY ARD i3 G2 Lost Framing S ARD = AR or ARL Figure 42 State Machine LT-S ...
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G1 deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM G2 pending activation As ...
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Test mode - TM2 Continuous alternating pulses are sent on the S/T-interface. • Command Abbr. Deactivation Request DR Reset RES Send Single Pulses TM1 Send Continuous TM2 Pulses Activation Request AR Activation Request ARL Loop Deactivation DC Confirmation Indication Abbr. ...
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S-Transceiver Enable / Disable The layer-1 part of the S-transceiver can be enabled/disabled with the two bits S_CONF0.DIS_TR and S_CONF2.DIS_TX. If DIS_TX=’1’ the transmit buffers are disabled. The receiver will monitor for incoming data in this configuration. By default ...
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Interrupt Structure S-Transceiver • S_STA 7 RINF 0 FECV 0 FSYN SQRR MSYN 7 MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 SQXR 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 Figure 43 Interrupt ...
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Operational Description 3.1 Layer 1 Activation/Deactivation 3.1.1 Generation of 4B3T Signal Elements For control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by TS 102 080 and FTZ 1 TR 220. Table 25 4B3T ...
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Table 25 4B3T Signal Elements (cont’ indicates that the whole link to the TE is synchronous in both directions. On detecting U3 the LT requests the NT by U4H to establish a fully transparent connection. The M-channel on ...
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Table 26 Generation of the 4B3T Signal Elements (cont’d) U4H Table 27 S/T-Interface Signals Signals from INFO 0 No signal. INFO 2 Frame with all bits and D-echo ...
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Complete Activation Initiated by Exchange • IOM â S/T-Reference Point INFO INFO 0 INFO 2 AR INFO 3 INFO 4 AI AR8/10 SBCX-X or IPAC-X Figure 44 Activation Initiated by Exchange Note: The LT ...
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Complete Activation Initiated by TE • â IOM -2 TE S/T-Reference Point INFO INFO 0 TIM PU AR8/10 INFO 1 INFO 2 RSY INFO 0 AR INFO 3 INFO 4 AI SBCX-X or IPAC-X Figure 45 ...
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Complete Activation Initiated by NT • IOM â S/T-Reference Point INFO INFO 0 INFO 2 AR INFO 3 INFO 8/10 SBCX-X or IPAC-X Figure 46 Activation Initiated by NT Note: The ...
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Complete Deactivation • â IOM -2 TE S/T-Reference Point INFO INFO 3 INFO 0 RSY DR INFO SBCX-X or IPAC-X Figure 47 Complete Deactivation Data Sheet NT U-Reference Point ...
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Loop 2 • â IOM -2 TE S/T-Reference Point INFO 4 AI AR8/10 INFO 3 SBCX-X or IPAC-X Figure 48 Loop 2 Note: Closing/resolving loop 2 may provoke the S-transceiver to resynchronize. In this case, the following C/I-codes are ...
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Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 49. • ® IOM -2 ...
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The S/T interface level detector is enabled, i. level is detected this will be reported by the Resynchronization Indication (RSY) but the loop function is not affected. Depending on the DIS_TX bit in the S_CONF2 register the internal ...
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Complete Loopback When receiving the request for a complete loopback, the U transceiver passes the downstream device, e.g. the S-bus transceiver. This is achieved by issuing the C/I- code AIL in the “Transparent” state or C/I ...
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LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 LOOP.U/IOM= Analog Part Digital Part Line Interface Unit DAC Echo Canceller PDM + ADC Filter Timing Recovery U-Transceiver Bandgap, Bias, Refer. Figure 52 Loopbacks Featured by Register LOOP Data Sheet & 1 2B1Q Scrambler A ...
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External Circuitry 3.3.1 Power Supply Blocking Recommendation The following blocking circuitry is suggested. • VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 1) 100nF VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) These capacitors should be located as near to the pins ...
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AOUT BIN AIN BOUT Figure 54 External Circuitry U-Transceiver with External Hybrid U-Transformer Parameters The following table lists parameters of typical U-transformers. Table 28 U-Transformer Parameters U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductanc of windings ...
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Resistors of the External Hybrid R3, R4 and 1. 1 Resistors COMP T • Optional use of trafos with non negligible resistance R resistors R depending ...
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S-Transformer Parameters The following Table 29 lists parameters of a typical S-transformer: Table 29 S-Transformer Parameters Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line ...
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SX1 SX2 Figure 55 External Circuitry S-Interface Transmitter Receiver The receiver of the S-transceiver is symmetrical recommended in each receive path preferable to split the resistance into two resistors for each line. This allows to ...
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Oscillator Circuitry Figure 57 illustrates the recommended oscillator circuit. • Figure 57 Crystal Oscillator Table 30 Crystal Parameters Parameter Frequency Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load ...
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Register Description 4.1 Address Space Figure 58 Address Space 4.2 Interrupts Special events in the T-SMINT which requests the host to read status information from the T-SMINT â from/to the T-SMINT I. Since only one INT request output is ...
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MASKU 1 CI RDS 1ms MASK ISTA CIC CIC 0 1 WOV WOV S S MOS MOS 0 1 INT â Figure 59 T-SMINT I Interrupt Status Registers â After the T-SMINT ...
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Register Summary r(0) = reserved, implemented as zero CI Handler Name 7 6 MODEH 1 1 CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 Data Sheet reserved 0 r(0) 0 DIM2 reserved CIC0 CIC1 TBA2 TBA1 CODR1 ...
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S-Transceiver Name DIS_ BUS CONF0 TR S_ DIS_ 0 CONF2 TX S_STA RINF S_CMD XINF SQRR MSYN MFEN SQXR 0 MFEN ISTAS 0 x MASKS MODE Data Sheet ...
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Interrupt, General Configuration Name 7 6 ISTA U ST MASK U ST CIC MODE1 MCLK CDS MODE2 LED2 LED1 LEDC SRES 0 0 RES_ CI/TIC Data Sheet CIC 0 WOV S 1 WOV ...
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IOM Handler (Timeslot, Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 CDA11 CDA20 CDA21 CDA_ DPS 0 TSDP10 CDA_ DPS 0 TSDP11 CDA_ DPS 0 TSDP20 CDA_ DPS 0 TSDP21 S_ DPS 0 TSDP_ B1 ...
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IOM Handler (Control Registers, Synchronous Transfer Interrupt Control) Name 7 6 S_CR 1 CI_CS CI_CR DPS_ EN_ CI1 CI1 MON_ DPS EN_ CR MON SDS1_ ENS_ ENS_ CR TSS TSS+1 SDS2_ ENS_ ENS_ CR TSS TSS+1 IOM_CR SPU 0 MCDA ...
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MONITOR Handler Name 7 6 MOR MOX MOSR MDR MER MOCR MRE MRC MSTA 0 0 MCONF 0 0 Data Sheet MONITOR Receive Data MONITOR Transmit Data MDA MAB 0 0 MIE MXC ...
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U-Transceiver Name 7 6 OPMODE 0 UCI UCIR 0 0 UCIW 0 0 LOOP 0 0 RDS ISTAU 0 CI MASKU 1 CI FW_ VERSION Note: Registers, which are denoted as ‘reserved‘, may not be accessed by the µC, neither ...
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Table 31 Reset of U-Transceiver Functions During Deactivation or with C/I- Code RESET Register Affected Bits/ Comment LOOP only the bits LBBD, LB2 and LB1 are reset 4.3.2 Mode Register Evaluation Timing Table 32 lists registers, which are evaluated ...
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Detailed C/I Registers 4.4.1 MODEH - Mode Register IOM-2 MODEH Value after reset DIM2-0 Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit enables/disables the ...
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CODR0 C/I0 Code Receive Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive IOM-frames and the previous code has been read from CIR0. CIC0 C/I0 Code Change 0 = ...
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CIX0 - Command/Indication Transmit 0 CIX0 Value after reset CODX0 CODX0 C/I0-Code Transmit Code to be transmitted in the C/I-channel 0. The code is only transmitted if the TIC bus is occupied, otherwise “1s” are transmitted. ...
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CODR1 C/I1-Code Receive CICW C/I-Channel Width Contains the read back value from CIX1 register (see below bit C/I1 channel width bit C/I1 channel width CI1E C/I1-channel Interrupt Enable Contains the read back value ...
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The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. However, in write direction the full CODX1 code is transmitted, i.e. the host must write the higher ...
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L1SW Enable Layer 1 State Machine in Software 0 = Layer 1 state machine of the T-SMINT 1 = Layer 1 state machine is disabled. The functionality must be realized in software. The commands are written to register S_CMD and ...
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RINF Important: This register is used only if the Layer 1 state machine of the device is disabled (S_CONF0:L1SW = 1) and implemented in software! With the layer 1 state machine enabled, the signals from this register are automatically ...
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Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine of the device is disabled (S_CONF0.L1SW = 1) and implemented in software! With the device layer 1 state machine enabled, the signals from ...
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MSYN MFEN MSYN Multi-frame Synchronization State 0 = The S/T receiver has not synchronized to the received F bits 1 = The S/T receiver has synchronized to the received F MFEN Multiframe Enable Read-back of the MFEN bit of ...
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ISTAS - Interrupt Status Register S-Transceiver ISTAS Value after reset These bits are set if an interrupt status occurs and an interrupt signal is activated if the corresponding mask bit is set to “0”. ...
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The S channel data for the next multiframe is writable. The register for the S bits to be transmitted has to be written within the next multiframe. This bit is reset by writing register SQXR. ...
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DCH_ D-Channel Inhibit INH 0 = inactive 1 = The S-transceiver blocks the access to the D-channel inverting the E-bits. MODE Mode Selection 000 = reserved 001 = reserved 010 = NT (without D-channel handler) 011 = ...
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ST Synchronous Transfer 0 = inactive 1 = This interrupt enables the microcontroller to lock on to the IOM timing, for synchronous transfers. CIC C/I Channel Change 0 = inactive change in C/I0 channel or C/I1 channel ...
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U ST Bit 7..0 Mask bits 0 = Interrupt is not masked 1 = Interrupt is masked Each interrupt source in the ISTA register can be selectively masked by setting the corresponding bit in MASK to ‘1’. Masked interrupt ...
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CDS Clock Divider Selection 0 = The 15.36 MHz oscillator clock divided by two is input to the MCLK prescaler 1 = The 15.36 MHz oscillator clock is input to the MCLK prescaler. WTC1, 2 Watchdog Timer Control 1, 2 ...
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MODE2 - Mode2 Register MODE2 Value after reset LED2 LED1 LED2,1 LED Control on pin ACT 00 = High 01 = flashing 1 flashing ...
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DESIGN Design Number The design number (DESIGN) allows to identify different hardware 1) designs of the T-SMINT 100000: Version 1.1 1) Distinction of different firmware versions is also possible by readingregister (7D) U-transceiver (see Chapter 4.9.8). 4.6.6 ...
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CDAxy 7 Data register CDAxy which can be accessed by the controller. Register Value after Reset CDA10 FF H CDA11 FF H CDA20 FF H CDA21 FF H 4.7.2 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy XXX_TSDPxy ...
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DPS Data Port Selection 0 = The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional unit XXX is input from DU The data channel xy of the ...
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The input of the CDAx1, CDAx0 register is disabled 1 = The input of the CDAx1, CDAx0 register is enabled EN_O1, Enable Output CDAx1, CDAx0 EN_O0 0 = The output of the CDAx1, CDAx0 register is disabled 1 ...
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EN_D Enable Transceiver D-Channel Data 0 = The corresponding data path to the transceiver is disabled 1 = The corresponding data path to the transceiver is enabled. EN_B2R Enable Transceiver B2 Receive Data (transmitter receives from IOM The ...
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DPS_CI1 EN_CI1 DPS_CI1 Data Port Selection CI1 Handler 0 = The CI1 data is output on DD and input from The CI1 data is output on DU and input from DD EN_CI1 Enable CI1 Handler 0 ...
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The MONITOR data is output on MON1 10 = The MONITOR data is output on MON2 11 = Not defined 4.7.7 SDS1_CR - Control Register Serial Data Strobe 1 SDS1_CR Value after reset ENS_ ENS_ ...
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TSS Timeslot Selection Selects one of 12 timeslots on the IOM during which SDS1 is active high. The data strobe signal allows standard data devices to access a programmable channel. 4.7.8 SDS2_CR - Control Register Serial Data Strobe 2 SDS2_CR ...
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TSS Timeslot Selection Selects one of 12 timeslots on the IOM during which SDS2 is active high. The data strobe signal allows standard data devices to access a programmable channel. 4.7.9 IOM_CR - Control Register IOM Data IOM_CR Value after ...
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DIS_IOM Disable IOM DIS_IOM should be set to ‘1’ if external devices connected to the IOM interface should be “disconnected” e.g. for power saving purposes. However, the T-SMINT bit The IOM interface is enabled 1 = The IOM ...
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For all interrupts in the STI register the following logical states are applied 0 = Interrupt has not occurred 1 = Interrupt has occurred STOVxy Synchronous Transfer Overflow Interrupt Enabled STOV interrupts for a certain STIxy interrupt are generated when ...
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MSTI - Mask Synchronous Transfer Interrupt MSTI Value after reset STOV21 STOV20 STOV11 STOV10 For the MSTI register the following logical states are applied Interrupt is not masked 1 = Interrupt is masked STOVxy ...
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MOX - MONITOR Transmit Channel MOX Value after reset Contains the MONITOR data to be transmitted in IOM to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by setting the monitor channel select ...
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MONITOR channel Data Abort 4.8.4 MOCR - MONITOR Control Register MOCR Value after reset MRE MRC MRE MONITOR Receive Interrupt Enable 0 = MONITOR interrupt status MDR generation is masked ...
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MSTA - MONITOR Status Register MSTA Value after reset MAC MONITOR Transmit Channel Active data transmission in the MONITOR channel 1 = The data transmission in the MONITOR channel is in ...
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Detailed U-Transceiver Registers 4.9.1 OPMODE - Operation Mode Register The Operation Mode register determines the operating mode of the U-transceiver. OPMODE Reset value UCI UCI Enable/Disable µP-control of C/I codes 0 = µP control ...
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UCIW Reset value 4.9.4 LOOP - Loopback Register The Loop register controls local digital loopbacks of the U-transceiver. LOOP Reset value TRANS Transparent/ Non-Transparent Loopback In transparent mode ...
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LBBD Close complete loop (B1, B2, D) near the system interface – the direction towards which the loop is closed is determined by bit U/IOM – the state machine has state ’Transparent’ first (e.g. by C/I = ...
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ISTAU Reset value C/I code indication the CI interrupt is generated independently on OPMODE.UCI 0 = inactive code change has occurred RDS Code violation occurred 0 = inactive 1 = ...
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Bit 0..7 Mask bits 0 = interrupt active 1 = interrupt masked 4.9.8 FW_VERSION FW_VERSION Register contains the Firmware Version number FW_VERSION Reset value Data Sheet read Firmware Version Number 159 PEF 82902 ...
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Electrical Characteristics 5.1 Absolute Maximum Ratings • Parameter Ambient temperature under bias Storage temperature Maximum Voltage Maximum Voltage on any pin with respect to ground ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV Note: Stress above those ...
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DC Characteristics • 3.3 V +/- DDA Digital Parameter Pins All Input low voltage Input high voltage All except Output low voltage DD/DU ACT,LP2I Output high voltage MCLK DD/DU Output low voltage ...
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Requirement ITU-T I.430, chapter 8.5.1.1b): ’When transmitting a binary zero, the output impedance shall be > 20 .’: Must be met by external circuitry. 3) Requirement ITU-T I.430, chapter 8.5.1.1b), Note: ’The output impedance limit shall apply for a ...
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Capacitances = 25 °C, 3 • Table 36 Pin Capacitances Parameter Digital pads: Input Capacitance I/O Capacitance Analog pads: Load Capacitance 5.4 Power Consumption • Power Consumption VDD=3.3 V, VSS=0 V, Inputs at ...
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Figure 60 Maximum Sinusoidal Ripple on Supply Voltage Data Sheet Electrical Characteristics 60 80 100 Frequency / kHz Frequency Ripple 164 PEF 82902 ITD04269.vsd 2001-11-09 ...
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AC Characteristics = - ° 3 Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V ...
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IOM -2 Interface • DCL DU/DD (Input DU/DD (Output DU/DD bit n (Output SDS1,2 ® Figure 62 IOM -2 Interface - Bit Synchronization Timing • FSC t 10 DCL BCL t 14 ...
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Parameter ® IOM -2 Interface DCL period DCL high DCL low Input data setup Input data hold Output data from high impedance to active (FSC high or other than first timeslot) Output data from active to high impedance Output ...
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Serial µP Interface • SCLK t 6 SDR SDX Figure 64 Serial Control Interface • Parameter SCI Interface SCLK cycle time SCLK high time SCLK low time CS setup time CS hold time SDR setup time ...
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Parallel µP Interface Siemens/Intel Bus Mode • AD0 - AD7 Figure 65 Microprocessor Read Cycle • AD0 - AD7 Figure 66 Microprocessor Write Cycle • ALE ...
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Figure 68 Non-Multiplexed Address Timing Motorola Bus Mode • Figure 69 Microprocessor Read Timing • ...
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Figure 71 Non-Multiplexed Address Timing Microprocessor Interface Timing • Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time ...
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ISTAU, FEBE and NEBE. However, the time RI between two consecutive read accesses to one of the registers ISTAU, FEBE or NEBE, respectively, must be longer than 330ns. ...
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Reset Table 37 Reset Input Signal Characteristics Parameter Symbol Length of active t RST low state Delay time for access after RST rising edge • RST Figure 72 Reset Input Signal Data Sheet Limit Values min. ...
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Undervoltage Detection Characteristics • HYS V DET V DDmin RSTO Figure 73 Undervoltage Control Timing Table 38 Parameters of the UVD/POR Circuit V = 3.3 V ± ...
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V = 3.3 V ± Parameter Delay for activation of RSTO Delay for deactivation of RSTO 1) The Detection Threshold V DET ® T-SMINT . Therefore, the board designer must take ...
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Package Outlines • Plastic Package, P-MQFP-64 (Metric Quad Flat Package) Data Sheet 176 PEF 82902 Package Outlines 2001-11-09 ...
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Plastic Package, P-TQFP-64 (Thin Quad Flat Package) Data Sheet 177 PEF 82902 Package Outlines 2001-11-09 ...
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Appendix: Differences between Q- and T-SMINT â The Q- and T-SMINT I have been designed compatible as possible. However, some differences between them are unavoidable due to the different line codes 2B1Q and 4B3T used for ...
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Pinning 7.1.1 Pin Definitions and Functions • Table 40 Pin Definitions and Functions Pin T/MQFP- 7.1.2 LED Pin ACT The 4 LED states (off, fast flashing, slow flashing, on), which can be displayed with pin ACT, ...
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U-Transceiver 7.2.1 U-Interface Conformity • Table 42 Related Documents to the U-Interface ETSI: TS 102 080 ANSI: T1.601-1998 (Revision of ANSI T1.601- 1992) CNET: ST/LAA/ELR/DNP/ 822 RC7355E FTZ-Richtlinie 1 TR 220 FTZ TS 0284/96 ’Intelligenter Netzabschluss (iNT)’ März 2001 ...
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U-Transceiver State Machines • SN0 T14S Pending Timing Any State T14S SSP or SP C/I= 'SSP' SN0 Any State Pin-RST or ARL C/I= 'RES' SN1 EC-Training AL SN3 Wait for SF AL SN3T Analog Loop Back Pend Receive Res. ...
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SN0 T14S Pending Timing DC Any State T14S DI SSP or SP C/I= 'SSP' Test DR SN0 Reset Any State DR Pin-RST or ARL C/I= 'RES' SN1 EC-Training AL DR SN3 Wait for SN3T Analog Loop ...
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T6S T6E Awake Signal Sent T13E Ack. Sent / Received T12S U1A (U0 & T12E) Synchronizing RSY SBC Synchronizing LOF AR / ARL Wait for Info U4H LOF AR / ARL U4H U5 ...
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Command/Indication Codes Table 43 C/I Codes Code Q-SMINT IN 0000 TIM 0001 RES 0010 – 0011 – 0100 EI1 0101 SSP 0110 DT 0111 – 1000 AR 1001 – 1010 ARL 1011 – 1100 AI 1101 – 1110 – ...
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Interrupt Structure • M56R 7 0 OPMODE.MLT MS2 MS1 + NEBE MFILT M61 CRC, TLL, M52 no Filtering M51 0 FEBE M4R MFILT 7 AIB UOA M46 CRC, TLL, M45 no M44 Filtering SCO DEA 0 ACT EOCR MFILT ...
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UCIR C/I C/I C/I 0 C/I intstruct_4b3t.emf Figure 78 Interrupt Structure U-Transceiver T-SMINT Data Sheet Appendix: Differences between Q- and T-SMINT‚I ISTAU MASKU RDS RDS ...
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Register Summary U-Transceiver U-Interface Registers Q-SMINT Name 7 6 OPMODE 0 UCI MFILT M56 FILTER EOCR EOCW M4RMASK M4WMASK M4R verified M4 bit data of last received superframe M4W M4 bit ...
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Name 7 6 ISTAU MLT CI MASKU MLT CI FW_ VERSION Data Sheet Appendix: Differences between Q- and T-SMINT‚ FEBE/ M56 M4 EOC NEBE FEBE/ M56 M4 EOC NEBE reserved FW Version Number reserved 188 PEF ...