PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 94

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S data will be inserted at the downstream (NT
(see
Interrupt Handling for Multi-Framing
To trigger the microcontroller for a multi-frame access an interrupt can be generated
once per multi-frame (SQW) or if the received Q-channel have changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
The start of a multiframe can not be synchronized to an external signal.
2.5.3
In the state G3 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register S_CMD is programmed to ’011’ the B1, B2 and D bits are transferred
transparently from the S/T to the IOM
are transmitted to the IOM
Note: In intelligent NT or intelligent LT-S mode the D-channel access can be blocked by
2.5.4
C/I commands ARL and AIL close the analog loop as close to the S-interface as possible.
ETSI refers to this loop under ’loopback 2’. ETSI requires, that B1, B2 and D channels
have the same propagation delay when being looped back.
The D-channel Echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). The
loop is transparent.
Note: After C/I-code AIL has been recognized by the S-transceiver, zeros are looped
2.5.5
The S-transceiver activation/ deactivation can be controlled by an internal statemachine
via the IOM
state the internal layer-1 statemachine of the S-transceiver is used. By setting the L1SW
bit in the S_CONF0 register the internal statemachine can be disabled and the layer-1
transmit commands, which are normally generated by the internal statemachine can be
written directly into the S_CMD register or the received status read out from the S_STA
register, respectively. The S-transceiver layer-1 control flow is shown in
Data Sheet
Table
the IOM
back in the B and D-channels (DU) for four frames.
Data Transfer between IOM
Loopback 2
Control of S-Transceiver / State Machine
24). Access to S2-S5-channel is not supported.
â
-2 C/I-channel or by software via the C interface directly. In the default
â
-2 D-channel handler.
â
-2 interface.
â
-2 interface and vice versa. In all other states ’1’s
82
â
-2 and S
TE) S bit position in each 5th S/T frame
0
Functional Description
Figure
PEF 82902
2001-11-09
39.