PEF2054NV21XT Infineon Technologies, PEF2054NV21XT Datasheet - Page 12

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

34
33
38
37
-
-
1.3
EPIC-S EPIC
17
6
5
4
3
9
11
13
15
8
10
12
14
Semiconductor Group
Pin No.
17
6
5
4
3
9
11
13
15
8
10
12
14
34
33
38
37
36 *
35 *
Pin Definitions and Functions (cont’d)
Symbol Input (I)
PDC
RxD0
RxD1
RxD2
RxD3
TxD0
TxD1
TxD2
TxD3
TSC0
TSC1
TSC2
TSC3
FSC
DCL
DU0/SIP4
DU1/SIP5
DU2/SIP6
DU3/SIP7
Output (O)
I
I
I
I
I
O
O
O
O
O
O
O
O
I/O
I/O
I/IO (OD)
I/IO (OD)
I/IO (OD)
I/IO (OD)
Function
PCM Interface Data Clock
Single or double data rate.
Receive PCM Interface Data
Time-slot oriented data is received on this pins
and forwarded into the downstream data memory
of the EPIC.
Transmit PCM Interface Data
Time slot oriented data is shifted out of the
EPIC’s upstream data memory on this lines. For
time-slots which are flagged in the tristate
data memory or when bit OMDR:PSB is reset
the pins are set to high impedance state.
Tristate Control
Supplies a control signal for an external driver.
These lines are “low” when the corresponding
TxD outputs are valid. During reset these lines
are “high”.
Frame Synchronization
Input or output in IOM configuration. Direction
indication signal in SLD mode.
Data Clock
Input or output in IOM, slave clock in SLD
configuration. In IOM configuration single or
double data rate, single data rate in SLD mode.
Data Upstream Input; IOM or PCM configuration.
Serial Interface Port, SLD configuration.
Depending on the bit OMDR:COS these lines
have push pull or open drain characteristic.
For unassigned channels or when bit
OMDR:CSB is reset the pins are in the state
high impedance.
* Note: EPIC-1 only
12
PEB 2055
PEF 2055
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