PEF2054NV21XT Infineon Technologies, PEF2054NV21XT Datasheet - Page 245

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

If the PCM input clock timing of figure 88 applies, the following values have to be written
to the EPIC to obtain the correct PCM and CFI timing:
EPIC
PBNR
POFD
POFU
PCSR
CMD1
CMD2
CBNR
CTAR
CBSR
CSCR
Figure 88
IOM
PMOD
Semiconductor Group
®
PFS/FSC
(8 kHz)
PDC
(2.048 MHz)
TxD#
(2.048 Mbit/s)
RxD#
(2.048 Mbit/s)
DCL
(1.536 MHz)
DD#
(768 kbit/s)
DU#
(768 kbit/s)
-2 (768 kbit/s) and PCM (2.048 Mbit/s) Timing Example
®
= 0010 0000
= 1111 1111
= 1111 0000
= 0001 1000
= 0000 0001
= 1110 0000
= 0000 0000
= 0101 1111
= 0000 0010
= 0010 0000
= 0000 0000
TS12,
TS31 Bit 1
TS31
,
,Bit 1
TS12, Bit 0
Bit 0
TS31
TS31 Bit 0
,Bit 0
,
B
B
B
B
B
B
B
B
B
B
B
TS0 Bit 7
TS0
= 20
= FF
= F0
= 18
= 01
= E0
= 00
= 5F
= 02
= 20
= 00
,Bit 7
,
TS0, Bit 7
TS0
TS0 Bit 6
TS0,
H
H
H
H
H
H
H
,
,Bit 6
H
H
H
H
Bit 7
TS0 Bit 5
TS0
PCM mode 0, single rate clock, PFS
evaluated with rising clock edge,
PCM comparison disabled
256 bits (32 ts) per PCM frame
PFS marks downstream PCM TS0, bit 7
PFS marks upstream PCM TS0, bit 7
PCM data received with falling, transmitted
with rising clock edge
DCL/FSC clock source, FSC evaluated with
rising clock edge, prescaler = 1, CFI mode 0
CFI data transmitted with rising, received with
falling clock edge
96 bits (12 ts) per CFI frame
PFS marks downstream CFI TS0
PFS marks downstream CFI bit 7, upstream
bits not shifted
64, 32, 16 kbit/s channels located on CFI bits
7 … 0, 7 … 4, 7 … 6
,
,Bit 5
245
TS0 Bit 4
TS0
TS0,
,
,Bit 4
TS0, Bit 6
Bit 6
TS0 Bit 3
TS0
,
,Bit 3
TS0 Bit 2
TS0
,
,Bit 2
TS0,
TS0 Bit 1
TS0
,
,Bit 1
TS0, Bit 5
Bit 5
TS0 Bit 0
TS0
,
,Bit 0
Application Hints
TS0 Bit 7
TS0
,
,Bit 7
TS0,
TS0 Bit 6
TS0
PEB 2055
TS0, Bit 4
PEF 2055
Bit 4
,
,Bit 6
ITT09560