HI1-565ATD-2 Intersil, HI1-565ATD-2 Datasheet - Page 9

• Manufacturer Part Number: HI1-565ATD-2
• Description: CONV D/A 12BIT 6.7MHZ 24-DIP
• Manufacturer: Intersil

Specifications of HI1-565ATD-2

• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 250mW
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

SEATING
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
NOTES:
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
PLANE
PLANE
1. Index area: A notch or a pin one identification mark shall be locat-
2. The maximum limits of lead dimensions b and c or M shall be
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
5. Dimension Q shall be measured from the seating plane to the
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
BASE
ccc
S1
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
M applies to lead plating and finish thickness.
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
base plane.
nearest metallization or lead.
b2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
M
bbb
C A - B
b
S
C A - B
For information regarding Intersil Corporation and its products, see web site www.intersil.com
S
A
D
-A-
-B-
A
D
S
e
S
D
9
S
S2
-D-
E
-C-
aaa
Q
M
A
M
e
c1
A/2
L
C A - B
SECTION A-A
LEAD FINISH
METAL
BASE
(b)
b1
S
M
e
c
A
D
S
(c)
D24.6
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
SYMBOL
eA/2
aaa
bbb
ccc
eA
S1
S2
b1
b2
b3
c1
Q
M
A
D
E
α
N
b
c
e
L
MIL-STD-1835 CDIP2-T24 (D-3, CONFIGURATION C)
0.014
0.014
0.045
0.023
0.008
0.008
0.500
0.120
0.015
0.005
0.005
MIN
90
-
-
-
-
-
-
0.100 BSC
0.600 BSC
0.300 BSC
o
INCHES
24
0.225
0.026
0.023
0.065
0.045
0.018
0.015
1.290
0.610
0.200
0.075
0.015
0.030
0.010
0.0015
MAX
105
-
-
o
12.70
0.36
0.36
1.14
0.58
0.20
0.20
3.05
0.38
0.13
0.13
MIN
MILLIMETERS
90
-
-
-
-
-
-
15.24 BSC
o
2.54 BSC
7.62 BSC
24
32.77
15.49
5.72
0.66
0.58
1.65
1.14
0.46
0.38
5.08
1.91
0.38
0.76
0.25
0.038
MAX
105
-
-
o
Rev. 0 4/94
NOTES
2
3
4
2
3
5
6
7
2
8
-
-
-
-
-
-
-
-
-
-
-
-