MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 70

• Manufacturer Part Number: MT46H8M32LFB5-6IT:H
• Description: MICMT46H8M32LFB5-6_IT:H MDDDR
• Manufacturer: Micron Technology Inc

Figure 32: Data Input Timing
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Notes:
Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as
shown in Figure 42 (page 79) and Figure 43 (page 80). Note that only the data-in
pairs that are registered prior to the
subsequent data-in should be masked with DM, as shown in Figure 42 (page 79) and
Figure 43 (page 80). After the PRECHARGE command, a subsequent command to the
same bank cannot be issued until
DQS
DM
CK#
DQ
CK
1. WRITE command issued at T0.
2.
3.
4. For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con-
4
5
t
t
controls DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
t
WPRES
T0
t
1
DQSS
t DS
T1
D
b
IN
t
WPRE
t
DSH
t DH
70
T1n
2
t
Transitioning Data
t
DQSL
DSS
t
256Mb: x16, x32 Mobile LPDDR SDRAM
RP is met.
t
WR period are written to the internal array, and any
3
T2
t
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
DQSH
DSH
T2n
2
t
t
WPST
DSS
3
T3
Don’t Care
© 2008 Micron Technology, Inc. All rights reserved.
WRITE Operation