MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 76

• Manufacturer Part Number: MT46H8M32LFB5-6IT:H
• Description: MICMT46H8M32LFB5-6_IT:H MDDDR
• Manufacturer: Micron Technology Inc

Figure 39: WRITE-to-READ – Interrupting
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
4
5
4
5
4
5
WRITE
Bank a,
Col b
T0
Notes:
t
t
t
1,2
DQSS
DQSS
DQSS
1. An interrupted burst of 4 is shown; 2 data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. D
D
b
IN
t
NOP
WTR is referenced from the first positive CK edge after the last data-in pair.
D
T1
IN
b
IN
b = data-in for column b; D
b+1
D
D
b
IN
IN
T1n
b+1
D
IN
b+1
D
IN
NOP
T2
t
WTR
T2n
3
76
Bank a,
READ
Col n
T3
OUT
256Mb: x16, x32 Mobile LPDDR SDRAM
n = data-out for column n.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
T4
Don’t Care
CL = 3
CL = 3
CL = 3
T5
NOP
© 2008 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
n
OUT
n
OUT
n
T6
NOP
D
n + 1
D
n + 1
D
n + 1
OUT
OUT
T6n
OUT