AD1859JR Analog Devices Inc, AD1859JR Datasheet
AD1859JR
Specifications of AD1859JR
Available stocks
Related parts for AD1859JR
AD1859JR Summary of contents
Page 1
FEATURES Complete, Low Cost Stereo DAC System in a Single Die Package Variable Rate Oversampling Interpolation Filter Multibit Modulator with Triangular PDF Dither Discrete and Continuous Time Analog Reconstruction Filters Extremely Low Out-of-Band Energy 64 Step (1 dB/Step) Analog ...
Page 2
AD1859–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages ( Ambient Temperature Input Clock (F ) MCLK Input Signal Input Sample Rate Measurement Bandwidth Input Data Word Width Load Capacitance Input Voltage ...
Page 3
DIGITAL TIMING (Guaranteed over – +105 BCLK HI Pulse Width DBH t BCLK LO Pulse Width DBL t BCLK Period DBP t LRCLK Setup DLS t LRCLK Hold (DSP Serial Port Style Mode Only) DLH ...
Page 4
... Model Range Description AD1859JR – +105 C 28-Lead SOIC AD1859JRS – +105 C 28-Lead SSOP CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1859 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
Page 5
DEFINITIONS Dynamic Range The ratio of a full-scale output signal to the integrated output noise in the passband ( kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and is equal to ...
Page 6
AD1859 Analog Signals Pin Name Number I/O Description FILT 28 O Voltage reference filter capacitor connection. Bypass and decouple the voltage reference with paral- lel 10 F and 0.1 F capacitors to the FGND pin. FGND 27 I Voltage reference ...
Page 7
The AD1859 has a simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The serial data input port can ...
Page 8
AD1859 Option for Analog De-emphasis Processing The AD1859 includes three pins for implementing an external analog 50/15 s (or possibly the CCITT J. 17) de-emphasis fre- quency response characteristic. A control pin DEEMP (Pin 2) enables de-emphasis when it is ...
Page 9
Figure 3 shows the I S-justified mode. LRCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition but with ...
Page 10
AD1859 CCLK CDATA D7 D6 MSB CLATCH MSB DATA7 LEFT/RIGHT Right Channel = HI Mute = HI Left Channel = LO Normal = LO The serial control port is byte oriented. The data is MSB first, and is unsigned. There ...
Page 11
AD1859 has been designed to minimize pops and clicks when muting and unmuting the device. The AD1859 includes a zero crossing detector which attempts to implement attenuation changes on waveform zero crossings only zero crossing is not found ...
Page 12
AD1859 Figure 15 shows the suggested interface to the Zoran ZR38000 DSP chip, which can act as an MPEG audio or AC-3 audio decoder. The ZR38000 supports 16 bits of data using a left- justified output format. SCKB ZORAN WSB ...
Page 13
PCB and Ground Plane Recommendations The AD1859 ideally should be located above a split ground plane, with the digital pins over the digital ground plane, and the analog pins over the analog ground plane. The split should occur between Pins ...
Page 14
AD1859 TYPICAL PERFORMANCE Figures 24 through 27 illustrate the typical analog performance of the AD1859 as measured by an Audio Precision System One. Signal-to-Noise (dynamic range) and THD+N performance is shown under a range of conditions. Note that there is ...
Page 15
FREQUENCY – Hz Figure 30. 1 kHz Tone at –90 dBFS (16K-Point FFT) ...
Page 16
AD1859 13 N [12.. [12..0] 13-BIT ADDER 13 + Figure 33. Numerically Controlled Oscillator Circuit 28-Lead Wide-Body SO (R-28) 0.7125 (18.10) 0.6969 (17.70 0.1043 (2.65) PIN 1 0.0926 (2.35) 0.0500 0.020 (0.49) 0.0118 ...