XC56309AG100A Freescale Semiconductor, XC56309AG100A Datasheet - Page 72

• Manufacturer Part Number: XC56309AG100A
• Description: IC DSP 24BIT 100MHZ 144-TQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309AG100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
4-14
* The MD–MA bits reflect the corresponding value of the mode input (that is, MODD–MODA), respectively.
Bit Number
9–8
3–0
10
7
6
5
4
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Name
CDP[1–0]
MD–MA
EBD
MS
SD
BE
Reset Value
11
0
0
0
0
0
*
DSP56309 User’s Manual, Rev. 1
Cache Burst Mode Enable
Enables/disables Burst mode in the memory expansion port during an
instruction cache miss. If the bit is cleared, Burst mode is disabled and only
one program word is fetched from the external memory when an instruction
cache miss condition is detected. If the bit is set, Burst mode is enabled, and
up to four program words are fetched from the external memory when an
instruction cache miss is detected.
Core-DMA Priority
Specify the priority of core and DMA accesses to the external bus.
Memory Switch Mode
Allows some internal data memory (X, Y, or both) to become part of the chip
internal Program RAM.
Notes: 1.
Stop Delay Mode
Determines the length of the delay invoked when the core exits the Stop
state. The STOP instruction suspends core processing indefinitely until a
defined event occurs to restart it. If SD is cleared, a 128 K clock cycle delay
is invoked before a STOP instruction cycle continues. However, if SD is set,
the delay before the instruction cycle continues is 16 clock cycles. The long
delay allows a clock stabilization period for the internal clock to begin
oscillating and to stabilize. When a stable external clock is used, the shorter
delay allows faster start-up of the DSP56300 core.
Reserved. Write to zero for future compatibility.
External Bus Disable
Disables the external bus controller to reduce power consumption when
external memories are not used. When EBD is set, the external bus
controller is disabled and external memory cannot be accessed. When EBD
is cleared, the external bus controller is enabled and external access can be
performed. Hardware reset clears the EBD bit.
Chip Operating Mode
Indicate the operating mode of the DSP56300 core. On hardware reset,
these bits are loaded from the external mode select pins, MODD, MODC,
MODB, and MODA, respectively. After the DSP56300 core leaves the Reset
state, MD–MA can be changed under program control.
00
01
10
11
2.
3.
Program data placed in the Program RAM/Instruction Cache
area changes its placement after the OMR[MS] bit is set (that
is, the Instruction Cache always uses the highest internal
program RAM addresses).
To ensure proper operation, place six NOP instructions after
the instruction that changes the MS bit.
To ensure proper operation, do not set the MS bit while the
Instruction Cache is enabled (SR[CE] bit is set).
Determined by comparing status register CP[1–0] to the active
DMA channel priority
DMA accesses have higher priority than core accesses
DMA accesses have the same priority as the core accesses
DMA accesses have lower priority than the core accesses
Description
Freescale Semiconductor