0W888-002-XTP ON Semiconductor, 0W888-002-XTP Datasheet - Page 15

• Manufacturer Part Number: 0W888-002-XTP
• Description: DSP BELASIGNA 250 AUDIO 64LFBGA
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 250r
• Type: Floating Pointr

Specifications of 0W888-002-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 50MHz
• On-chip Ram: 42kB
• Voltage - I/o: 1.0V, 2.0V
• Voltage - Core: 1.00V, 2.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFBGA
• Package: 64LFBGA
• Numeric And Arithmetic Format: Fixed-Point
• Ram Size: 16 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -

accumulate (MAC) architecture that feeds into a 40−bit
accumulator complete with barrel shifter for fast
normalization and de−normalization operations. Program
execution is controlled by a sequencer that employs a
three−stage pipeline (FETCH, DECODE, EXECUTE).
Furthermore, the RCore incorporates pointer configuration
registers for low cycle−count address generation when
accessing the three memories: program memory (PRAM),
X data memory (XRAM) and Y data memory (YRAM).
Instruction Set
following three classes:
1. Arithmetic and Logic Instructions
data format. Thus, the range of valid numbers is [−1; 1),
which is represented by 0x8000 to 0x7FFF. Other formats
can be utilized by applying appropriate shifts to the data.
multiplication every time an operand is loaded into either the
X or Y registers. A number of instructions that allow loading
of X and Y simultaneously and addition of the new product
to the previous product (a MAC operation) are available.
Single−cycle MAC with data pointer update and fetch is
supported.
The RCore is a single−cycle pipelined multiply−
The RCore instruction set can be divided into the
The RCore uses two’s−complement fractional as a native
The multiplier takes 16−bit values and performs a
PH
X
Multiplier
AE AH
Limiter
PL
Y
AL
Internal Routing
ALU
Shifter
Barrel
DCU
EXP
Figure 3. RCore DSP Architecture
ST
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Internal Routing
Immediate
LC0
PCU
LC1
15
either the accumulator (AE|AH|AL) or the product register
(PH|PL). Although the RCore is a 16−bit system, 32−bit
additions or subtractions are also supported. Bit
manipulation is also available on the accumulator, as are
operations to perform arithmetic or logic shifting, toggling
of specific bits, limiting, and other functions.
2. Data Movement Instructions
control registers and the RCore’s internal registers
(accumulator, PH, PL, etc.).
generate two addresses in a single cycle. The address
pointers R0..2 and R4..6 can be configured to support
increment, decrement, add−by−offset, and two types of
modulo−N circular buffer operations. Single−cycle access
to low−X memory or low−Y memory as well as two−cycle
instructions for immediate access to any address, are also
available.
3. Program Flow Control Instructions
instructions and larger segments of code using dedicated
repeat instructions or hardware loop counters. Furthermore,
instructions to manipulate the program counter (PC) register
such as calls to subroutines, conditional branches and
unconditional branches are also provided.
The arithmetic logic unit (ALU) receives its input from
Data movement instructions transfer data between RAM,
Two address generators are available to simultaneously
The RCore supports repeating of both single−word
The full instruction set may be seen in Table 8.
REP
PRAM
PC
D_AUX_REG0
D_AUX_REG4
EXT3
D_INT_STATUS
D_INT_EBL
D_SYS_CTRL
CTRL
P_Bus
Data registers
Address and Control registers
X_Bus
Y_Bus
R0
R1
R2
R3
R4
R5
R6
R7
XRAM
X_AGU
YRAM
Y_AGU
PCFG0
PCFG1
PCFG2
PCFG4
PCFG5
PCFG6