EP1SGX10DF672I6 Altera, EP1SGX10DF672I6 Datasheet - Page 161

• Manufacturer Part Number: EP1SGX10DF672I6
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 362
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
February 2005
pin. The I/O standards supported by any particular bank determines
what standards are possible for an external clock output driven by the fast
PLL in that bank.
Table 4–20
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5V HSTL class I
1.5V HSTL class II
SSTL-18 class I
SSTL-18 class II
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
SSTL-3 class II
AGP (1× and 2× )
CTT
Table 4–20. Fast PLL Port Input Pin I/O Standards
shows the I/O standards supported by fast PLL input pins.
I/O Standard
Stratix GX Device Handbook, Volume 1
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix GX Architecture
Input
PLLENABLE
v
v
4–95