XC4VFX100-10FFG1517C Xilinx Inc, XC4VFX100-10FFG1517C Datasheet - Page 250

• Manufacturer Part Number: XC4VFX100-10FFG1517C
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517C

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
250
IOStandard Attribute
Output Slew Rate Attributes
Output Drive Strength Attributes
Lower Capacitance I/O Attributes
The IOSTANDARD attribute is available to choose the values for an I/O standard for all
I/O buffers. The supported I/O standards are listed in
attribute uses the following syntax in the UCF file:
The IOSTANDARD default for single-ended I/O is LVCMOS25, for differential I/Os the
default is LVDS_25.
A variety of attribute values provide the option of choosing the desired slew rate for
single-ended I/O output buffers. For LVTTL and LVCMOS output buffers (OBUF, OBUFT,
and IOBUF), the desired slew rate can be specified with the SLEW attribute.
The allowed values for the SLEW attribute are:
•
•
The SLEW attribute uses the following syntax in the UCF file:
By the default, the slew rate for each output buffer is set to SLOW. This is the default used
to minimize the power bus transients when switching non-critical signals.
For LVTTL and LVCMOS output buffers (OBUF, OBUFT, and IOBUF), the desired drive
strength (in mA) can be specified with the DRIVE attribute.
The allowed values for the DRIVE attribute are:
•
•
•
•
•
•
•
The DRIVE attribute uses the following syntax in the UCF file:
To lower the effective input capacitance, some I/O resources do not have differential
driver circuits (LVDS_25, LVDSEXT_25, LVDS_25_DCI, LVDSEXT_25_DCI, ULVDS_25,
RSDS_25, and LDT_25). Using these I/Os improves the signal integrity of high-speed clock
inputs. Differential inputs and all output standards other than these are still supported by
low capacitance I/Os. Refer to
The allowed values for the CAPACITANCE attribute are:
•
INST <I/O_BUFFER_INSTANTIATION_NAME> IOSTANDARD=”<IOSTANDARD VALUE>”;
SLEW = SLOW (Default)
SLEW = FAST
INST <I/O_BUFFER_INSTANTIATION_NAME> SLEW = "<SLEW_VALUE>";
DRIVE = 2
DRIVE = 4
DRIVE = 6
DRIVE = 8
DRIVE = 12 (Default)
DRIVE = 16
DRIVE = 24
INST <I/O_BUFFER_INSTANTIATION_NAME> DRIVE = "<DRIVE_VALUE>";
DONT_CARE (Default)
www.xilinx.com
“Clock Capable I/O” in Chapter 1
Table
UG070 (v2.6) December 1, 2008
6-38. The IOSTANDARD
Virtex-4 FPGA User Guide
for further information.
R