XC4VFX100-10FFG1517C Xilinx Inc, XC4VFX100-10FFG1517C Datasheet - Page 367

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XC4VFX100-10FFG1517C

Manufacturer Part Number
XC4VFX100-10FFG1517C
Description
IC FPGA VIRTEX-4FX 100K 1517FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX100-10FFG1517C

Number Of Logic Elements/cells
94896
Number Of Labs/clbs
10544
Total Ram Bits
6930432
Number Of I /o
768
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Part Number:
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Part Number:
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0
Table 8-1: ISERDES Port List and Definitions
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
O
Q1 – Q6
SHIFTOUT1
SHIFTOUT2
BITSLIP
CE1, CE2
CLK
CLKDIV
D
Port Name
ISERDES Primitive
R
Output
Output
Output
Output
Input
Input
Input
Input
Input
Type
Figure 8-2
Table 8-1
1 (each)
1 (each)
Width
1
1
1
1
1
1
1
REV
BITSLIP
CE1
CE2
CLK
CLKDIV
D
DLYCE
DLYINC
DLYRST
OCLK
SHIFTIN1
SHIFTIN2
SR
lists the available ports in the ISERDES primitive.
shows the ISERDES primitive.
Combinatorial output.
Registered outputs.
Carry out for data width expansion. Connect to SHIFTIN1 of slave IOB.
See
Carry out for data width expansion. Connect to SHIFTIN2 of slave IOB.
See
Invokes the Bitslip operation.
Clock enable inputs.
High-speed clock input. Clocks serial input data stream.
Divided clock input. Clocks delay element, deserialized data, Bitslip submodule,
and CE unit.
Serial input data from IOB.
“ISERDES Width Expansion.”
“ISERDES Width Expansion.”
www.xilinx.com
Figure 8-2: ISERDES Primitive
Input Serial-to-Parallel Logic Resources (ISERDES)
Description
UG70_8_02_031208
O
Q1
Q2
Q3
Q4
Q5
Q6
SHIFTOUT1
SHIFTOUT2
367

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