XCV812E-8FG900C Xilinx Inc, XCV812E-8FG900C Datasheet - Page 17

• Manufacturer Part Number: XCV812E-8FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-8FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 8:
Table 9
each device.
Table 9:
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
For more detailed information on serial PROMs see the
PROM data sheet at
tions/ds026.pdf
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
Table 10:
DS025-2 (v2.3) November 19, 2002
Boundary-scan mode
SelectMAP mode
Slave-serial mode
CCLK
Configuration Mode
XCV405E
XCV812E
Device
lists the total number of bits required to configure
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
High time
Low time
Maximum Frequency
Frequency Tolerance, master mode with respect to nominal
R
Configuration Codes
Virtex-E Bitstream Lengths
Master/Slave Serial Mode Programming Switching
.
http://www.xilinx.com/bvdocs/publica-
M2
# of Configuration Bits
0
0
0
Description
M1
0
1
1
3,430,400
6,519,648
M0
1
0
1
CCLK Direction
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
N/A
In
In
www.xilinx.com
1-800-255-7778
ured, the data for the next device is routed to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
The change of DOUT on the rising edge of CCLK differs
from previous families but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
Figure 13
device in slave-serial mode should be connected as shown
in the right-most device.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected. However, it is recommended to drive the con-
figuration
slave-serial mode programming switching characteristics.
Table 10
shown in
INIT pins of all daisy-chained FPGAs are High.
Data Width
References
1
8
1
Figure
Figure
provides more detail about the characteristics
shows a full master/slave system. A Virtex-E
1/2
1/2
mode
3
4
5
Serial D
14. Configuration must be delayed until the
Yes
pins
No
No
T
T
DSCK
Symbol
DCC
out
T
T
T
F
CCO
CCH
CCL
CC
externally.
/T
/T
CCD
CKDS
Configuration Pull-ups
+45% –30%
Values
5.0/0.0
5.0/0.0
12.0
Figure 14
5.0
5.0
66
Yes
Yes
Yes
Module 2 of 4
MHz, max
ns, max
ns, min
ns, min
ns, min
ns, min
Units
shows
13