CY7C63743-SXC Cypress Semiconductor Corp, CY7C63743-SXC Datasheet - Page 19

• Manufacturer Part Number: CY7C63743-SXC
• Description: IC MCU 8K USB/PS2 LS 24SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63743-SXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 16
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1622

Bit 5: OUT Received
Bit 4: ACKed Transaction
Bit [3:0]: Mode Bit[3:0]
USB Non-control Endpoints
The CY7C637xxC feature two non-control endpoints, endpoint 1
(EP1) and endpoint 2 (EP2). The EP1 and EP2 Mode Registers
do not have the locking mechanism of the EP0 Mode Register.
The EP1 and EP2 Mode Registers use the format shown in
Figure
0xF0–0xF7, EP2 uses an 8-byte FIFO at SRAM locations
0xE8–0xEF as shown in Section .
Figure 17. USB Endpoint EP1, EP2 Mode Registers (Ad-
dresses 0x14 and 0x16)
Document #: 38-08022 Rev. *D
Name
Read/
Reset
Write
Bit #
Bit
modes give the firmware total control on how to respond to
different tokens sent to the endpoints from the host.
In addition, the Mode Bits are automatically changed by the
SIE in response to many USB transactions. For example, if
the Mode Bit [3:0] are set to 1011 which is ACK OUT-NAK IN
mode as shown in
Mode Bit [3:0] to NAK IN/OUT (0001) mode after issuing an
ACK handshake in response to an OUT token. Firmware
needs to update the mode for the SIE to respond appropriate-
ly.
1 = A valid OUT packet has been received. This bit is updated
to ‘1’ after the last received packet in an OUT transaction. This
bit is cleared by any non-locked writes to the register.
0 = No OUT received. This bit is cleared by any non-locked
writes to the register.
The ACKed Transaction bit is set whenever the SIE engages
in a transaction to the register's endpoint that completes with
an ACK packet.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
The endpoint modes determine how the SIE responds to USB
traffic that the host sends to the endpoint. For example, if the
endpoint Mode Bits [3:0] are set to 0001 which is NAK IN/OUT
mode as shown in
in response to any IN or OUT token sent to this endpoint. In
this NAK IN/OUT mode, the SIE will send an ACK handshake
when the host sends a SETUP token to this endpoint. The
mode encoding is shown in
the mode bits can be found in
. EP1 uses an 8-byte FIFO at SRAM locations
STALL Reserved
R/W
7
0
6
0
-
Table
Table
5
0
-
Transaction
8, the SIE will send NAK handshakes
8, the SIE will change the endpoint
ACKed
Table
R/C
4
0
Table 9
8. Additional information on
R/W R/W R/W R/W
3
0
and
Mode Bit
2
0
Table
1
0
10. These
0
0
Bit 7: STALL
Bit [6:5]: Reserved. Must be written to zero during register writes.
Bit 4: ACKed Transaction
Bit [3:0]: Mode Bit [3:0]
USB Endpoint Counter Registers
There are three Endpoint Counter registers, with identical
formats for both control and non-control endpoints. These
registers contain byte count information for USB transactions, as
well as bits for data packet status. The format of these registers
is shown in Figure 18.
Figure 18. Endpoint 0,1,2 Counter Registers
(Addresses 0x11, 0x13 and 0x15)
Bit 7: Data Toggle
Bit 6: Data Valid
Read/Writ
Bit Name
1 = The SIE will stall an OUT packet if the Mode Bits are set
to ACK-OUT, and the SIE will stall an IN packet if the mode
bits are set to ACK-IN. See Section for the available modes.
0 = This bit must be set to LOW for all other modes.
The ACKed transaction bit is set whenever the SIE engages
in a transaction to the register's endpoint that completes with
an ACK packet.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
The EP1 and EP2 Mode Bits operate in the same manner as
the EP0 Mode Bits (see Section ).
This bit selects the DATA packet's toggle state. For IN trans-
actions, firmware must set this bit to the select the transmitted
Data Toggle. For OUT or SETUP transactions, the hardware
sets this bit to the state of the received Data Toggle bit.
1 = DATA1
0 = DATA0
This bit is used for OUT and SETUP tokens only. This bit is
cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred.
This bit does not update for some endpoint mode settings.
Refer to Table 10 for more details.
1 = Data is valid.
0 = Data is invalid. If enabled, the endpoint interrupt will occur
even if invalid data is received.
Reset
Bit #
e
Toggle
Data
R/W
7
0
Valid
Data
R/W
6
0
Reserved
5
0
-
4
0
-
CY7C63722C
CY7C63723C
CY7C63743C
R/
W
3
0
Byte Count
R/
W
2
0
Page 19 of 53
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W
1
0
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W
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