AT43USB326-AU Atmel, AT43USB326-AU Datasheet - Page 61

• Manufacturer Part Number: AT43USB326-AU
• Description: IC USB KEYBOARD CTRLR 48LQFP
• Manufacturer: Atmel
• Series: AVR®r

Specifications of AT43USB326-AU

• Applications: Keyboard Controller
• Core Processor: AVR
• Program Memory Type: Mask ROM (16 kB)
• Controller Series: AT43USB
• Ram Size: 512 x 8
• Interface: USB
• Number Of I /o: 32
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3313D–USB–04/06
Function Endpoint 1,2 Control and Acknowledge Register – FCAR1,2
• Bit 7 – Reserved
This bit is reserved in the AT43USB326 and will read as zero.
• Bit 6 – DATA END
When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last
data packet in FIFO, or that the microcontroller has processed the last data packet it expects
from the Host.
• Bit 5 – FORCE STALL
This bit is set by the microcontroller to indicate a stalled endpoint. The hardware will send a
STALL handshake as a response to the next IN or OUT token. The microcontroller sets this bit
if it wants to force a STALL. A STALL is send if the host continues to ask for data after the data
is exhausted.
• Bit 4 – TX PACKET RDY: Transmit Packet Ready
When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a
packet of data. This bit is cleared by the hardware after the USB Host acknowledges the
packet. For ISO endpoints, this bit is cleared unconditionally after the data is sent.
The microcontroller should write into the FIFO only if this bit is cleared. After it has completed
writing the data, it should set this bit. This data can be of zero length.
The hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX
Complete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to
the microcontroller.
• Bit 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt
Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is
not actually stored and thus does not have to be cleared.
• Bit 2 – Reserved
This bit is reserved in the AT43USB326 and will read as zero.
• Bit 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt
Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit
is not actually stored and thus does not have to be cleared.
• Bit 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt
Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is
not actually stored and thus does not have to be cleared.
Function EP1 $1FA4
Function EP2 $1FA3
Read/Write
Initial Value
Bit
R
7
–
–
0
DATA
DATA
END
END
R/W
6
0
FORCE
FORCE
STALL
STALL
R/W
0
5
TX PACKET
TX PACKET
RDY
RDY
R/W
4
0
STALL_SENT-
STALL_SENT-
ACK
ACK
R/W
3
0
R
2
–
–
0
RX_OUT_PACKET
RX_OUT_PACKET
_ACK
_ACK
R/W
AT43USB326
1
0
TX_COMPLETE
TX_COMPLETE
_ACK
-ACK
R/W
0
0
FCAR1
FCAR2
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