Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 44

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

ASCI Block Diagram
ASCI Registers
PS014004-1106
TXA
RXA
RTS
CTS
DCD
ASCI Transmit Shift Register 0 (TSR0, TSR1)—When the ASCI Transmit Shift
Register (
shifted out to the
automatically loaded from
available for transmission,
register is not program accessible.
ASCI Transmit Data Register 0,1 (TDR0, TDR1)— I/O
address =
transferred to the
the previous byte of data. The ASCI transmitter is double buffered.
0
0
0
0
0
ASCI Transmit Data Register
Ch 0: TDR0
ASCI Transmit Shift Register*
Ch 0: TSR0
ASCI Receive Data FIFO
Ch 0: RDR0
ASCI Receive Shift Register*
Ch 0: RSR0 (8)
ASCI Control Register A
Ch 0: CNTLA0 (8)
ASCI Control Register B
Ch 0: CNTB0 (8)
ASCI Status FIFO
Ch 0
ASCI Status Register
Ch 0: STAT0 (8)
TSR
06h, 07h
) receives data from the ASCI Transmit Data Register (
TxA
TSR
. Data written to the ASCI Transmit Data Register is
CKA
CKA
Figure 27. ASCI Block Diagram
pin. When transmission is completed, the next byte (if available) is
as soon as
0
1
TDR
TSR IDLE
Internal Address/Data Bus
Interrupt Request
into
TSR
Baud Rate
Generator 0
Baud Rate
Generator 1
ASCI
Control
TSR
s by outputting a continuous High level. This
is empty. Data can be written while
and the next transmission starts. If no data is
φ
ASCI Transmit Data Register
Ch 1: TDR1
ASCI Transmit Shift Register*
Ch 1: TSR1
ASCI Receive Data FIFO
Ch 1: RDR1
ASCI Receive Shift Register*
Ch 1: RSR1 (8)
ASCI Control Register A
Ch 1: CNTLA1 (8)
ASCI Control Register B
Ch 1: CNTB1 (8)
ASCI Status FIFO
Ch 1
ASCI Status Register
Ch 1: STAT1 (8)
Note: *Not Program
Accessible.
Microprocessor Unit
TDR
TXA
RXA
CTS
TSR
), the data is
1
1
1
is shifting out
Architecture
Z80180
38