Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 74

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

TRAP Timing—2
PS014004-1106
A
0
–A
nd
Op Code Undefined
18
D
MREQ
(A
0
Note:
When a
1. The
2. The current Program Counter (
3. The Z80180 vectors to logical address
All
the prefix opcodes
following one of the double-prefix opcodes
The state of the Undefined Fetch Object (
adjust the stacked
ated the
stacked
PC-2
–D
WR
RD
M1
19
φ
7
)
TRAP
opcode, is saved on the stack.
.
T
PC-1
If logical address 0000h is mapped to physical address 00000h, the vector is the
same as for RESET. In this case, testing the TRAP bit in ITC reveals whether the
restart at physical address 00000h was caused by RESET or TRAP.
TRAP
TRAP
TRAP
1
2nd Opcode
Fetch Cycle
interrupts occur after fetching an undefined second opcode byte following one of
Undefined
Opcode
T
Figure 70. TRAP Timing—2
2
. If
. If
interrupt occurs, the Z80180 operates as follows:
bit in the Interrupt
T
3
UFO = 1
UFO = 0
PC
T
CBh
TP
, depending on whether the second or third byte of the opcode gener-
T
i
,
, the starting address of the invalid instruction is equal to the stacked
PC
DDh
T
, the starting address of the invalid instruction is equal to the
i
,
T
EDh
i
T
TRAP
i
, or
PC
T
) value, reflecting the location of the undefined
i
FDh
/Control (
T
nd
UFO
1
, or after fetching an undefined third opcode byte
0
Opcode Undefined
T
DDCBh
.
2
SP-1
PC
) bit in
T
PC Stacking
H
3
ITC
T
or
1
ITC
) register is set to
FDCBh
T
2
SP-2
PC
allows
T
L
3
.
T
1
TRAP
Restart
from 0000h
Opcode
Fetch Cycle
T
2
0000h
Microprocessor Unit
T
3
software to correctly
1
.
Architecture
Z80180
68